From patchwork Wed May 18 23:30:25 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Gerlach X-Patchwork-Id: 9122981 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 8D4089F37F for ; Wed, 18 May 2016 23:32:24 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8CE4720340 for ; Wed, 18 May 2016 23:32:23 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8AAF520306 for ; Wed, 18 May 2016 23:32:22 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1b3Avl-0004zI-8C; Wed, 18 May 2016 23:31:09 +0000 Received: from comal.ext.ti.com ([198.47.26.152]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1b3Avi-0004Aw-7u for linux-arm-kernel@lists.infradead.org; Wed, 18 May 2016 23:31:07 +0000 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id u4INUbbQ022524; Wed, 18 May 2016 18:30:37 -0500 Received: from DLEE70.ent.ti.com (dlemailx.itg.ti.com [157.170.170.113]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id u4INUb6p014814; Wed, 18 May 2016 18:30:37 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.294.0; Wed, 18 May 2016 18:30:36 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id u4INUbX9025573; Wed, 18 May 2016 18:30:37 -0500 Received: from localhost (uda0274052.am.dhcp.ti.com [128.247.83.19]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id u4INUa319081; Wed, 18 May 2016 18:30:37 -0500 (CDT) From: Dave Gerlach To: , , , , Subject: [PATCH 1/2] Documentation: dt: add bindings for ti-cpufreq Date: Wed, 18 May 2016 18:30:25 -0500 Message-ID: X-Mailer: git-send-email 2.7.3 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160518_163106_411656_62ED11B8 X-CRM114-Status: GOOD ( 15.30 ) X-Spam-Score: -8.3 (--------) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Nishanth Menon , Dave Gerlach , Tony Lindgren , Viresh Kumar , "Rafael J . Wysocki" , Yegor Yefremov , Rob Herring Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add the device tree bindings document for the TI CPUFreq/OPP driver on AM33xx and AM43xx SoCs. The operating-points-v2 binding allows us to provide an opp-supported-hw property for each OPP to define when it is available. This driver is responsible for reading and parsing registers to determine which OPPs can be selectively enabled based on the specific SoC in use by matching against the opp-supported-hw data. Signed-off-by: Dave Gerlach --- .../devicetree/bindings/cpufreq/ti-cpufreq.txt | 89 ++++++++++++++++++++++ 1 file changed, 89 insertions(+) create mode 100644 Documentation/devicetree/bindings/cpufreq/ti-cpufreq.txt diff --git a/Documentation/devicetree/bindings/cpufreq/ti-cpufreq.txt b/Documentation/devicetree/bindings/cpufreq/ti-cpufreq.txt new file mode 100644 index 000000000000..f719b2df2a1f --- /dev/null +++ b/Documentation/devicetree/bindings/cpufreq/ti-cpufreq.txt @@ -0,0 +1,89 @@ +Bindings for TI's CPUFreq driver +================================ + +The ti-cpufreq driver works with the operating-points-v2 binding described +at [../opp/opp.txt] to make sure the proper OPPs for a platform get enabled +and then creates a "cpufreq-dt" platform device to leverage the cpufreq-dt +driver described in [cpufreq-dt.txt]. + +Certain TI SoCs, like those in the am335x, am437x, am57xx, and dra7xx +families support different OPPs depending on the silicon variant in use. +The ti-cpufreq driver uses the revision and an efuse value from the SoC to +provide the OPP framework with supported hardware information. This is used +to determine which OPPs from the operating-points-v2 table get enabled. In +order to maintain backwards compatilibity if this information is not present +the "cpufreq-dt" platform device is still created to attempt to find an +operating-points (v1) table, otherwise no OPPs will be available because +safe OPPs cannot be determined. + +Required properties: +-------------------- +In 'cpus' nodes: +- operating-points-v2: Phandle to the operating-points-v2 table to use +- ti,syscon-efuse: Syscon phandle, offset to efuse register, efuse register + mask, and efuse register shift to get the relevant bits + that describe OPP availability +- ti,syscon-rev: Syscon and offset used to look up revision value on SoC + +In 'operating-points-v2' table: +- opp-supported-hw: Two bitfields indicating: + 1. Which revision of the SoC the OPP is supported by + 2. Which eFuse bits indicate this OPP is available + + A bitwise and is performed against these values and if any bit + matches, the OPP gets enabled. + +NOTE: Without the above, platform-device for "cpufreq-dt" is still created + but no determination of which OPPs should be available is done, but this + allows for use of a v1 operating-points table. + +Example: +-------- + +/* From arch/arm/boot/dts/am4372.dtsi */ +cpus { + cpu: cpu@0 { + ... + + operating-points-v2 = <&cpu0_opp_table>; + + ti,syscon-efuse = <&scm_conf 0x610 0x3f 0>; + ti,syscon-rev = <&scm_conf 0x600>; + + ... + }; +}; + +cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp50@300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <950000>; + opp-supported-hw = <0xFF 0x01>; + opp-suspend; + }; + + opp100@600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1100000>; + opp-supported-hw = <0xFF 0x04>; + }; + + opp120@720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-microvolt = <1200000>; + opp-supported-hw = <0xFF 0x08>; + }; + + oppturbo@800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1260000>; + opp-supported-hw = <0xFF 0x10>; + }; + + oppnitro@1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1325000>; + opp-supported-hw = <0xFF 0x20>; + }; +};