| Message ID | fa3b1df7fc5e74f375df5de53061d1a93d154b51.1566471985.git.agx@sigxcpu.org (mailing list archive) |
|---|---|
| State | Mainlined |
| Commit | 215701807e53a379e1c9b2e6401676779ef85ea0 |
| Headers | show |
| Series | arch: arm64: imx8mq: Add mux-controller to iomuxc_gpr | expand |
On Thu, 2019-08-22 at 13:10 +0200, Guido Günther wrote: > The only mux controls the MIPI DSI input selection. > > Signed-off-by: Guido Günther <agx@sigxcpu.org> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> regards Philipp > --- > arch/arm64/boot/dts/freescale/imx8mq.dtsi | 9 ++++++++- > 1 file changed, 8 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > index 4fdd60f2c51e..3f3594d9485c 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > @@ -440,8 +440,15 @@ > }; > > iomuxc_gpr: syscon@30340000 { > - compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon"; > + compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", > + "syscon", "simple-mfd"; > reg = <0x30340000 0x10000>; > + > + mux: mux-controller { > + compatible = "mmio-mux"; > + #mux-control-cells = <1>; > + mux-reg-masks = <0x34 0x00000004>; /* MIPI_MUX_SEL */ > + }; > }; > > ocotp: ocotp-ctrl@30350000 {
On Thu, Aug 22, 2019 at 01:10:23PM +0200, Guido Günther wrote: > The only mux controls the MIPI DSI input selection. > > Signed-off-by: Guido Günther <agx@sigxcpu.org> Applied, thanks.
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 4fdd60f2c51e..3f3594d9485c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -440,8 +440,15 @@ }; iomuxc_gpr: syscon@30340000 { - compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon"; + compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", + "syscon", "simple-mfd"; reg = <0x30340000 0x10000>; + + mux: mux-controller { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x34 0x00000004>; /* MIPI_MUX_SEL */ + }; }; ocotp: ocotp-ctrl@30350000 {
The only mux controls the MIPI DSI input selection. Signed-off-by: Guido Günther <agx@sigxcpu.org> --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-)