From patchwork Fri May 27 18:54:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 12863694 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E48CEC433F5 for ; Fri, 27 May 2022 18:54:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234223AbiE0Syc (ORCPT ); Fri, 27 May 2022 14:54:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46928 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344367AbiE0Sy3 (ORCPT ); Fri, 27 May 2022 14:54:29 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 49C794C78F for ; Fri, 27 May 2022 11:54:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1653677668; x=1685213668; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=AntRebEHO2QXwXqacg8Qi8Pr5uztpIkYtQzBGp8BPug=; b=TBLM1ObPB4BjqOxmLTp4JdGLKnY4rArJzgkreEorPtHZcTgT8XvK2YFp Xfk1mVS/VpMd6tgrzFvYRx+/3QTDB3Z9si1rt4UoCjUNywOH752pobqVv W/tR7G28bnQOmVIBJ3sEZFypLNKUYHdaWjyIHPYWeO6R9c9oky6aU1iFv Y=; Received: from unknown (HELO ironmsg05-sd.qualcomm.com) ([10.53.140.145]) by alexa-out-sd-02.qualcomm.com with ESMTP; 27 May 2022 11:54:28 -0700 X-QCInternal: smtphost Received: from nasanex01b.na.qualcomm.com ([10.46.141.250]) by ironmsg05-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 May 2022 11:54:28 -0700 Received: from JESSZHAN.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Fri, 27 May 2022 11:54:27 -0700 From: Jessica Zhang To: CC: Jessica Zhang , , , , , , , , Subject: [PATCH 0/3] Expand CRC to support interface blocks Date: Fri, 27 May 2022 11:54:04 -0700 Message-ID: <20220527185407.162-1-quic_jesszhan@quicinc.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Refactor existing CRC code for layer mixer and add CRC support for interface blocks Jessica Zhang (3): drm/msm/dpu: Separate LM-specific CRC code from generic CRC code drm/msm/dpu: Add MISR register support for interface drm/msm/dpu: Add interface support for CRC debugfs drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 115 +++++++++++++++----- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 3 + drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 61 +++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 22 ++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 55 +++++++++- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 8 +- 6 files changed, 233 insertions(+), 31 deletions(-)