Message ID | 20221001190807.358691-1-marijn.suijten@somainline.org (mailing list archive) |
---|---|
Headers | show |
Series | drm: Fix math issues in MSM DSC implementation | expand |
On 01-10-22, 21:08, Marijn Suijten wrote: > Various removals of complex yet unnecessary math, fixing all uses of > drm_dsc_config::bits_per_pixel to deal with the fact that this field > includes four fractional bits, and finally an approach for dealing with > dsi_host setting negative values in range_bpg_offset, resulting in > overflow inside drm_dsc_pps_payload_pack(). > > Note that updating the static bpg_offset array to limit the size of > these negative values to 6 bits changes what would be written to the DPU > hardware at register(s) DSC_RANGE_BPG_OFFSET, hence the choice has been > made to cover up for this while packing the value into a smaller field > instead. Thanks for fixing these. I dont have my pixel3 availble but changes lgtm Reviewed-by: Vinod Koul <vkoul@kernel.org> > Altogether this series is responsible for solving _all_ Display Stream > Compression issues and artifacts on the Sony Tama (sdm845) Akatsuki > smartphone (2880x1440p). Does it need two dsi lanes?
On 2022-10-04 10:12:58, Vinod Koul wrote: > On 01-10-22, 21:08, Marijn Suijten wrote: > > Various removals of complex yet unnecessary math, fixing all uses of > > drm_dsc_config::bits_per_pixel to deal with the fact that this field > > includes four fractional bits, and finally an approach for dealing with > > dsi_host setting negative values in range_bpg_offset, resulting in > > overflow inside drm_dsc_pps_payload_pack(). > > > > Note that updating the static bpg_offset array to limit the size of > > these negative values to 6 bits changes what would be written to the DPU > > hardware at register(s) DSC_RANGE_BPG_OFFSET, hence the choice has been > > made to cover up for this while packing the value into a smaller field > > instead. > > Thanks for fixing these. I dont have my pixel3 availble but changes lgtm > > Reviewed-by: Vinod Koul <vkoul@kernel.org> Thanks; any comment on the self-review I sent in for patch 3 and 5? > > Altogether this series is responsible for solving _all_ Display Stream > > Compression issues and artifacts on the Sony Tama (sdm845) Akatsuki > > smartphone (2880x1440p). > > Does it need two dsi lanes? This panel has the default of four dsi data lanes enabled: https://github.com/sonyxperiadev/kernel/blob/f956fbd9a234033bd18234d456a2c32c126b38f3/arch/arm64/boot/dts/qcom/dsi-panel-somc-akatsuki.dtsi#L74-L77 Unless you are referring to dual-dsi (ctrl/phy); this panel doesn't have a dual connection, but I do have devices on sm8350/sm8450 with a "4k"@120Hz display that have this, in case you want it to be tested? However, for the time being I'm focussing on a similar panel (4 data lanes, single DSI ctrl/phy) on sm8250 which keeps showing corrupted / garbled data and resulting in ping-pong timeouts. I haven't yet confirmed if this is due to the "integration" of the pingpong block with the intf (since relevant registers and interrupts still seem to be accessible), a mismatching resource topology, or a misconfiguration elswhere. Relevant panel dts if you're interested: https://github.com/sonyxperiadev/kernel/blob/e70161ec43b147b0b02578d05ab64552fd2df2cd/arch/arm64/boot/dts/somc/dsi-panel-sofef03_m-fhd_plus.dtsi - Marijn