From patchwork Wed Oct 11 09:00:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imran Shaik X-Patchwork-Id: 13416911 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 04482CD6E4B for ; Wed, 11 Oct 2023 09:00:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345054AbjJKJA5 (ORCPT ); Wed, 11 Oct 2023 05:00:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43648 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343913AbjJKJA5 (ORCPT ); Wed, 11 Oct 2023 05:00:57 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6191094; Wed, 11 Oct 2023 02:00:55 -0700 (PDT) Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 39B6psCB020160; Wed, 11 Oct 2023 09:00:47 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=/C1rFeXSlfNmwsrUVHhL8M4nqWlxSH6MFMqznyY8L5Q=; b=kfcesoxD5jFEPg01PNm0xT+soYNt6GXFrUfQM/5vNsh3+7DyhJItKaw6XN27eEizQ30F kZS2rbBCO7Ll6B6BrQwOc4Fvkw+zMMwpW5ZYSMsigNiN+4HYUddOrKlEf1YcgPOCVq0v 2JP9yYV3Tf54GbX9JKTZW1Z2V52+uRhZM7AtAXO3Uzbgo3Qxz2nCYTX5HxMJflYIUgjT CCn2YH4CfxKbzxBTUb1py+doxNeGPFjBJ+bgX0LSFTXUQ8woZLIRPWdF2JGMY9WyDRZA oWiz+N0YK3eKGGCMto7aQ4xu7zASwgUX7uQpkcpxqdaQDb0L4P8ASniu4BhxFI7tf/QK Sw== Received: from nasanppmta03.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3tne0q14e9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 11 Oct 2023 09:00:47 +0000 Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 39B90kAW032767 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 11 Oct 2023 09:00:46 GMT Received: from hu-imrashai-hyd.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.36; Wed, 11 Oct 2023 02:00:41 -0700 From: Imran Shaik To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Taniya Das , Imran Shaik , , , , , Ajit Pandey , Jagadeesh Kona Subject: [PATCH V2 0/4] Add support for Qualcomm ECPRI clock controller Date: Wed, 11 Oct 2023 14:30:24 +0530 Message-ID: <20231011090028.1706653-1-quic_imrashai@quicinc.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 63s3dS_WJpjPyG7JffCyGrxha6spo1_4 X-Proofpoint-ORIG-GUID: 63s3dS_WJpjPyG7JffCyGrxha6spo1_4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-11_06,2023-10-10_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 bulkscore=0 spamscore=0 mlxscore=0 clxscore=1011 priorityscore=1501 phishscore=0 adultscore=0 impostorscore=0 suspectscore=0 lowpriorityscore=0 mlxlogscore=922 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2309180000 definitions=main-2310110079 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The ECPRI clock controller support for QDU1000 and QRU1000. The clock controller has a special branch which requires an additional memory to be enabled/disabled before the branch ops. Changes since v1: - Updated the dt-bindings - Modified mem ops logic as per the review comments - Update all the hex values to lowercase - Aligned the clock entries in DT as per the review comment Previous series: v1 - https://patchwork.kernel.org/project/linux-arm-msm/list/?series=774092 Imran Shaik (3): dt-bindings: clock: qcom: Add ECPRICC clocks for QDU1000 and QRU1000 clk: qcom: Add ECPRICC driver support for QDU1000 and QRU1000 arm64: dts: qcom: qdu1000: Add ECPRI clock controller Taniya Das (1): clk: qcom: branch: Add mem ops support for branch2 clocks .../bindings/clock/qcom,qdu1000-ecpricc.yaml | 68 + arch/arm64/boot/dts/qcom/qdu1000.dtsi | 14 + drivers/clk/qcom/Kconfig | 8 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clk-branch.c | 37 + drivers/clk/qcom/clk-branch.h | 21 + drivers/clk/qcom/ecpricc-qdu1000.c | 2466 +++++++++++++++++ .../dt-bindings/clock/qcom,qdu1000-ecpricc.h | 147 + 8 files changed, 2762 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,qdu1000-ecpricc.yaml create mode 100644 drivers/clk/qcom/ecpricc-qdu1000.c create mode 100644 include/dt-bindings/clock/qcom,qdu1000-ecpricc.h