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[144.178.202.138]) by smtp.gmail.com with ESMTPSA id jw22-20020a170906e95600b00a4623030893sm3249098ejb.126.2024.03.13.05.53.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Mar 2024 05:53:30 -0700 (PDT) From: Luca Weiss Subject: [PATCH 0/2] Add Inline Crypto Engine for SC7280 UFS Date: Wed, 13 Mar 2024 13:53:13 +0100 Message-Id: <20240313-sc7280-ice-v1-0-3fa089fb7a27@fairphone.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIALmh8WUC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyDHUUlJIzE vPSU3UzU4B8JSMDI2NDIwML3eJkcyMLA93M5FTdRFNTAzMjs6S0ZANLJaCGgqLUtMwKsGHRsbW 1AFIEwhpcAAAA To: Bjorn Andersson , Konrad Dybcio , Herbert Xu , "David S. Miller" , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.13.0 Add the required bits to support Inline Crypto Engine on SC7280 SoC with UFS. Signed-off-by: Luca Weiss --- Luca Weiss (2): dt-bindings: crypto: ice: Document sc7280 inline crypto engine arm64: dts: qcom: sc7280: Add inline crypto engine .../devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml | 1 + arch/arm64/boot/dts/qcom/sc7280.dtsi | 9 +++++++++ 2 files changed, 10 insertions(+) --- base-commit: 5f19977109ce685937fee9feea9b807599dfc925 change-id: 20231208-sc7280-ice-a550626bfc09 Best regards,