| Message ID | 20240322-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v2-0-3ec0a966d52f@linaro.org (mailing list archive) |
|---|---|
| Headers | show |
| Series | arm64: qcom-sm8[456]50: properly describe the PCIe Gen4x2 PHY AUX clock | expand |
On Fri, 22 Mar 2024 10:42:37 +0100, Neil Armstrong wrote: > The PCIe Gen4x2 PHY found in the SM8[456]50 SoCs have a second clock named > "PHY_AUX_CLK" which is an input of the Global Clock Controller (GCC) which > is muxed & gated then returned to the PHY as an input. > > Document the clock IDs to select the PIPE clock or the AUX clock, > also enforce a second clock-output-names and a #clock-cells value of 1 > for the PCIe Gen4x2 PHY found in the SM8[456]50 SoCs. > > [...] Applied, thanks! [1/7] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: document PHY AUX clock on SM8[456]50 SoCs commit: 72bea132f3680ee51e7ed2cee62892b6f5121909 [2/7] phy: qcom: qmp-pcie: refactor clock register code commit: 677b45114b4430a43d2602296617efc4d3f2ab7a [3/7] phy: qcom: qmp-pcie: register second optional PHY AUX clock commit: 583ca9ccfa806605ae1391aafa3f78a8a2cc0b48 [4/7] phy: qcom: qmp-pcie: register PHY AUX clock for SM8[456]50 4x2 PCIe PHY commit: 5cee04a8369049b92d52995e320abff18dfeda44 Best regards,
The PCIe Gen4x2 PHY found in the SM8[456]50 SoCs have a second clock named "PHY_AUX_CLK" which is an input of the Global Clock Controller (GCC) which is muxed & gated then returned to the PHY as an input. Document the clock IDs to select the PIPE clock or the AUX clock, also enforce a second clock-output-names and a #clock-cells value of 1 for the PCIe Gen4x2 PHY found in the SM8[456]50 SoCs. The PHY driver needs a light refactoring to support a second clock, and finally the DT is changed to connect the PHY second clock to the corresponding GCC input then drop the dummy fixed rate clock. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- Changes in v2: - Collected review tags - Switched back to of_clk_add_hw_provider/devm_add_action_or_reset to maintain compatibility - Tried to use generic of_clk_hw_onecell_get() but it requires to much boilerplate code and would still need a local qmp_pcie_clk_hw_get() to support the current #clock-cells=0 when exposing 2 clocks, so it's simpler to just return the clocks in qmp_pcie_clk_hw_get() - Link to v1: https://lore.kernel.org/r/20240319-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v1-0-926d7a4ccd80@linaro.org --- Neil Armstrong (7): dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: document PHY AUX clock on SM8[456]50 SoCs phy: qcom: qmp-pcie: refactor clock register code phy: qcom: qmp-pcie: register second optional PHY AUX clock phy: qcom: qmp-pcie: register PHY AUX clock for SM8[456]50 4x2 PCIe PHY arm64: dts: qcom: sm8450: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk arm64: dts: qcom: sm8550: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk arm64: dts: qcom: sm8650: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk .../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 27 +++++- arch/arm64/boot/dts/qcom/sm8450.dtsi | 8 +- arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 4 - arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 4 - arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 8 -- arch/arm64/boot/dts/qcom/sm8550.dtsi | 13 +-- arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 4 - arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 4 - arch/arm64/boot/dts/qcom/sm8650.dtsi | 13 +-- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 98 ++++++++++++++++++++-- include/dt-bindings/phy/phy-qcom-qmp.h | 4 + 11 files changed, 133 insertions(+), 54 deletions(-) --- base-commit: 2e93f143ca010a5013528e1cfdc895f024fe8c21 change-id: 20240319-topic-sm8x50-upstream-pcie-1-phy-aux-clk-4b35169707dd Best regards,