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[78.88.45.141]) by smtp.gmail.com with ESMTPSA id xa4-20020a170906fd8400b00a5252e69c7dsm5905590ejb.160.2024.04.17.13.03.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Apr 2024 13:03:03 -0700 (PDT) From: Konrad Dybcio Subject: [PATCH v2 0/7] Add SMEM-based speedbin matching Date: Wed, 17 Apr 2024 22:02:52 +0200 Message-Id: <20240404-topic-smem_speedbin-v2-0-c84f820b7e5b@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAOwqIGYC/22NQQqDMBREryJ/3ZQkaJGueo8ixSSjfqiJJBJax Ls3Fbors3oD82ajhMhIdK02isicOPgC+lSRnXo/QrArTFrqWpaINSxsRZoxP9ICOMNetA6wTho MElSWS8TAr8N67wpPnNYQ38dJVt/252v++rISUlho015q3Sijbk/2fQznEEfq9n3/AOJYqwO3A AAA To: Bjorn Andersson , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Neil Armstrong , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1713384181; l=2910; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=DJ8DSD99sxYhrIfsLOLcFHZ/8SkT9S5JHfim2UIEGSk=; b=qPZ9W7adu9DGmD4JrUVkPIxmZpfCiw/Zfg4GfqJo5ewDABLjWBmW8KhtVN69tnCvwbjFzsZE8 wueUz4LeEDxDsH/1HVL2yf7+59ucDJZ5PQfqTXiOaOCFikruX6L3QLi X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Newer (SM8550+) SoCs don't seem to have a nice speedbin fuse anymore, but instead rely on a set of combinations of "feature code" (FC) and "product code" (PC) identifiers to match the bins. This series adds support for that. I suppose a qcom/for-soc immutable branch would be in order if we want to land this in the upcoming cycle. FWIW I preferred the fuses myself.. Patches 5 and 6 coooould be omitted, but I'd reaaally like them to land and soon at that. This would enable even more overdue and necessary cleanups/feature prepwork sooner than later. The dt patch can only be picked if the drm patches are there. Depends on: https://lore.kernel.org/linux-arm-msm/20240412-topic-adreno_nullptr_supphw-v1-1-eb30a1c1292f@linaro.org/ Signed-off-by: Konrad Dybcio --- Changes in v2: - Separate moving existing and adding new defines - Fix kerneldoc copypasta - Remove some wrong comments and defines - Remove assumed "max" values for PCs and external FCs - Improve some commit messages - Return -EOPNOTSUPP instead of -EINVAL when calling p/fcode getters on socinfo older than v16 - Drop pcode getters and evaluation (doesn't matter for Adreno on non-proto SoCs, might matter in the future or w/ other peripherals) - Rework the speedbin logic to be hopefully saner (accidental support for A2xx-A4xx, I guess!) - Reorder some existing function calls to avoid crazy nullptrs - ""fix"" the smem dependency inconvenience - Link to v1: https://lore.kernel.org/r/20240405-topic-smem_speedbin-v1-0-ce2b864251b1@linaro.org --- Konrad Dybcio (7): soc: qcom: Move some socinfo defines to the header soc: qcom: smem: Add a feature code getter drm/msm/adreno: Implement SMEM-based speed bin drm/msm/adreno: Add speedbin data for SM8550 / A740 drm/msm/adreno: Define A530 speed bins explicitly drm/msm/adreno: Redo the speedbin assignment arm64: dts: qcom: sm8550: Wire up GPU speed bin & more OPPs arch/arm64/boot/dts/qcom/sm8550.dtsi | 21 +++++- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 34 ---------- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 54 --------------- drivers/gpu/drm/msm/adreno/adreno_device.c | 13 ++++ drivers/gpu/drm/msm/adreno/adreno_gpu.c | 103 +++++++++++++++++++++++++---- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 11 +-- drivers/gpu/drm/msm/msm_gpu.c | 3 - drivers/soc/qcom/smem.c | 33 +++++++++ drivers/soc/qcom/socinfo.c | 8 --- include/linux/soc/qcom/smem.h | 1 + include/linux/soc/qcom/socinfo.h | 34 ++++++++++ 11 files changed, 198 insertions(+), 117 deletions(-) --- base-commit: b13768266bf3a129adf5bbd0bad28e23a74329a2 change-id: 20240404-topic-smem_speedbin-8deecd0bef0e Best regards,