Message ID | 20240521011946.3148712-1-quic_jiegan@quicinc.com (mailing list archive) |
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Tue, 21 May 2024 01:20:09 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 44L1K76Y013806 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 21 May 2024 01:20:07 GMT Received: from jiegan-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 20 May 2024 18:20:01 -0700 From: Jie Gan <quic_jiegan@quicinc.com> To: Mathieu Poirier <mathieu.poirier@linaro.org>, Suzuki K Poulose <suzuki.poulose@arm.com>, Alexander Shishkin <alexander.shishkin@linux.intel.com>, Konrad Dybcio <konradybcio@gmail.com>, Mike Leach <mike.leach@linaro.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> CC: Jinlong Mao <quic_jinlmao@quicinc.com>, Leo Yan <leo.yan@linaro.org>, "Greg Kroah-Hartman" <gregkh@linuxfoundation.org>, <coresight@lists.linaro.org>, <linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>, Tingwei Zhang <quic_tingweiz@quicinc.com>, Yuanfang Zhang <quic_yuanfang@quicinc.com>, Tao Zhang <quic_taozha@quicinc.com>, Trilok Soni <quic_tsoni@quicinc.com>, Song Chai <quic_songchai@quicinc.com>, <linux-arm-msm@vger.kernel.org>, <andersson@kernel.org>, <quic_yijiyang@quicinc.com>, <quic_yuanjiey@quicinc.com>, <quic_liuxin@quicinc.com> Subject: [PATCH v1 0/1] arm64: dts: qcom: Add coresight nodes for SA8775p Date: Tue, 21 May 2024 09:19:45 +0800 Message-ID: <20240521011946.3148712-1-quic_jiegan@quicinc.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: <linux-arm-msm.vger.kernel.org> List-Subscribe: <mailto:linux-arm-msm+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-arm-msm+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: hrTO-5BkPuDDcwlBbupm-evwRgTSEdCC X-Proofpoint-GUID: hrTO-5BkPuDDcwlBbupm-evwRgTSEdCC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.12.28.16 definitions=2024-05-20_13,2024-05-17_03,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 phishscore=0 clxscore=1011 mlxlogscore=667 suspectscore=0 spamscore=0 bulkscore=0 mlxscore=0 adultscore=0 lowpriorityscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2405010000 definitions=main-2405210009 |
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arm64: dts: qcom: Add coresight nodes for SA8775p
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On Tue, 21 May 2024 09:19:45 +0800, Jie Gan wrote: > Add coresight components for SA8775p. > The device tree change is checked by dtbs_check command and these components > all tested with SA8775p device. > > Jie Gan (1): > arm64: dts: qcom: Add coresight nodes for SA8775p > > [...] Applied, thanks! [1/1] arm64: dts: qcom: Add coresight nodes for SA8775p commit: 6596118ccdcdb3ec5e417293e43bf6b122363a37 Best regards,