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Sat, 3 Aug 2024 03:23:05 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 2 Aug 2024 20:23:00 -0700 From: Krishna chaitanya chundru Subject: [PATCH v2 0/8] PCI: Enable Power and configure the QPS615 PCIe switch Date: Sat, 3 Aug 2024 08:52:46 +0530 Message-ID: <20240803-qps615-v2-0-9560b7c71369@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAIairWYC/2XMQQ6CMBCF4auQWVtTBizFlfcwLLCdyiws0GqjI b27la3L/+Xl2yBSYIpwrjYIlDjy7EvgoQIzjf5Ogm1pQImt7LAT6xJVfRKEum/HRttGOSjnJZD j9w5dh9ITx+ccPrub8Lf+EQmFFNrc6t4q54p2WV9s2JujmR8w5Jy/AlE/iZ4AAAA= To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , , "Bartosz Golaszewski" , Jingoo Han , "Manivannan Sadhasivam" CC: , , , , , , "Bartosz Golaszewski" , Krishna chaitanya chundru X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1722655379; l=3676; i=quic_krichai@quicinc.com; s=20230907; h=from:subject:message-id; bh=6cavA9XLKIM3BgR3NHEgRZLrQUpWWMHMmofpuijT6oo=; b=/YzAIHJt439+4CTndqI64GLKUe1QJ+fWY+Q+exNah01wKp0y01ATu4qVq+WeA0K4HW1fifxxT BJwqwNcrHdGDGVWP5P8e6RtD+ucGDK8zx+1MibGYfErDaUNZuOgFfW5 X-Developer-Key: i=quic_krichai@quicinc.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: Y_v6DKcPIHw1qvNbDN5vkrATq5p704Ui X-Proofpoint-GUID: Y_v6DKcPIHw1qvNbDN5vkrATq5p704Ui X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-02_20,2024-08-02_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 impostorscore=0 malwarescore=0 suspectscore=0 phishscore=0 mlxscore=0 priorityscore=1501 lowpriorityscore=0 bulkscore=0 adultscore=0 spamscore=0 clxscore=1011 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408030020 QPS615 is the PCIe switch which has one upstream and three downstream ports. One of the downstream ports is used as endpoint device of Ethernet MAC. Other two downstream ports are supposed to connect to external device. One Host can connect to QPS615 by upstream port. QPS615 switch power is controlled by the GPIO's. After powering on the switch will immediately participate in the link training. if the host is also ready by that time PCIe link will established. The QPS615 needs to configured certain parameters like de-emphasis, disable unused port etc before link is established. The device tree properties are parsed per node under pci-pci bridge in the devicetree. Each node has unique bdf value in the reg property, driver uses this bdf to differentiate ports, as there are certain i2c writes to select particulat port. As the controller starts link training before the probe of pwrctl driver, the PCIe link may come up before configuring the switch itself. To avoid this introduce two functions in pci_ops to start_link() & stop_link() which will disable the link training if the PCIe link is not up yet. Now PCI pwrctl device is the child of the pci-pcie bridge, if we want to enable the suspend resume for pwrctl device there may be issues since pci bridge will try to access some registers in the config which may cause timeouts or Un clocked access as the power can be removed in the suspend of pwrctl driver. To solve this make PCIe controller as parent to the pci pwr ctrl driver and create devlink between host bridge and pci pwrctl driver so that pci pwrctl driver will go suspend only after all the PCIe devices went to suspend. Signed-off-by: Krishna chaitanya chundru --- Changes in V1: - Fix the code as per the comments given. - Removed D3cold D0 sequence in suspend resume for now as it needs seperate discussion. - change to dt approach for configuring the switch instead of request_firmware() approach - Link to v1: https://lore.kernel.org/linux-pci/20240626-qps615-v1-4-2ade7bd91e02@quicinc.com/T/ --- --- Krishna chaitanya chundru (8): dt-bindings: PCI: Add binding for qps615 dt-bindings: trivial-devices: Add qcom,qps615 arm64: dts: qcom: qcs6490-rb3gen2: Add node for qps615 PCI: Change the parent to correctly represent pcie hierarchy PCI: Add new start_link() & stop_link function ops PCI: dwc: Add support for new pci function op PCI: qcom: Add support for host_stop_link() & host_start_link() PCI: pwrctl: Add power control driver for qps615 .../devicetree/bindings/pci/qcom,qps615.yaml | 191 ++++++ .../devicetree/bindings/trivial-devices.yaml | 2 + arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 121 ++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- drivers/pci/bus.c | 3 +- drivers/pci/controller/dwc/pcie-designware-host.c | 18 + drivers/pci/controller/dwc/pcie-designware.h | 16 + drivers/pci/controller/dwc/pcie-qcom.c | 39 ++ drivers/pci/pwrctl/Kconfig | 7 + drivers/pci/pwrctl/Makefile | 1 + drivers/pci/pwrctl/core.c | 9 +- drivers/pci/pwrctl/pci-pwrctl-qps615.c | 638 +++++++++++++++++++++ include/linux/pci.h | 2 + 13 files changed, 1046 insertions(+), 3 deletions(-) --- base-commit: 1722389b0d863056d78287a120a1d6cadb8d4f7b change-id: 20240727-qps615-e2894a38d36f Best regards,