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Tue, 27 Aug 2024 06:36:44 +0000 Received: from NALASPPMTA01.qualcomm.com (NALASPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 47R6TpR3023742; Tue, 27 Aug 2024 06:36:43 GMT Received: from hu-devc-lv-u22-c.qualcomm.com (hu-qianyu-lv.qualcomm.com [10.81.25.114]) by NALASPPMTA01.qualcomm.com (PPS) with ESMTPS id 47R6ahKE006254 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 27 Aug 2024 06:36:43 +0000 Received: by hu-devc-lv-u22-c.qualcomm.com (Postfix, from userid 4098150) id A1DED64E; Mon, 26 Aug 2024 23:36:43 -0700 (PDT) From: Qiang Yu To: manivannan.sadhasivam@linaro.org, vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, andersson@kernel.org, konradybcio@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, abel.vesa@linaro.org, quic_msarkar@quicinc.com, quic_devipriy@quicinc.com Cc: dmitry.baryshkov@linaro.org, kw@linux.com, lpieralisi@kernel.org, neil.armstrong@linaro.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Qiang Yu Subject: [PATCH 0/8] Add support for PCIe3 on x1e80100 Date: Mon, 26 Aug 2024 23:36:23 -0700 Message-Id: <20240827063631.3932971-1-quic_qianyu@quicinc.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 4xFp7q55GvlXzYXFXY7WdbXka_FMOjgS X-Proofpoint-GUID: 4xFp7q55GvlXzYXFXY7WdbXka_FMOjgS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-27_04,2024-08-26_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 priorityscore=1501 spamscore=0 clxscore=1011 suspectscore=0 lowpriorityscore=0 mlxlogscore=972 impostorscore=0 phishscore=0 mlxscore=0 malwarescore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408270048 This series add support for PCIe3 on x1e80100. PCIe3 needs additional set of clocks, regulators and new set of PCIe QMP PHY configuration compare other PCIe instances on x1e80100. Hence add required resource configuration and usage for PCIe3. Qiang Yu (8): phy: qcom-qmp: pcs-pcie: Add v6.30 register offsets phy: qcom-qmp: pcs: Add v6.30 register offsets phy: qcom: qmp: Add phy register and clk setting for x1e80100 PCIe3 arm64: dts: qcom: x1e80100: Add support for PCIe3 on x1e80100 dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100 QMP PCIe PHY Gen4 x8 clk: qcom: gcc-x1e80100: Fix halt_check for pipediv2 clocks arm64: dts: qcom: x1e80100-qcp: Add power supply and sideband signal for pcie3 PCI: qcom: Add support to PCIe slot power supplies .../phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 18 +- arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 116 +++++++++ arch/arm64/boot/dts/qcom/x1e80100.dtsi | 205 +++++++++++++++- drivers/clk/qcom/gcc-x1e80100.c | 10 +- drivers/pci/controller/dwc/pcie-qcom.c | 52 +++- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 222 +++++++++++++++++- .../qualcomm/phy-qcom-qmp-pcs-pcie-v6_30.h | 25 ++ drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_30.h | 19 ++ 8 files changed, 657 insertions(+), 10 deletions(-) create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_30.h create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_30.h