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Wed, 9 Oct 2024 14:34:10 GMT Received: from hu-mahap-hyd.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 9 Oct 2024 07:34:03 -0700 From: Mahadevan Subject: [PATCH v4 0/5] Display enablement changes for Qualcomm SA8775P platform Date: Wed, 9 Oct 2024 20:02:00 +0530 Message-ID: <20241009-patchv3_1-v4-0-cd683a9ca554@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAOCTBmcC/03Myw6CMBCF4Vchs7ZkplwEV76HMaSOg50FFAsSE 8K7W125O19y8m8wS1SZ4ZRtEGXVWcOYUB4yYO/Ghxi9J4NFW2JboJncwn4tOjI1It+YqrKVBtJ /itLr+9e6XJP7GAaz+Cjur2BrIqTimFuLSFVjyDxfyt3gvJvO36kj5xwG2PcPpH4Cz50AAAA= X-Change-ID: 20240930-patchv3_1-600cbc1549e8 To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , "Maarten Lankhorst" , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mahadevan , Neil Armstrong , Bjorn Andersson , "Konrad Dybcio" CC: , , , , , Kalyan Thota , Jayaprakash Madisetty , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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It includes the addition of the hardware catalog, compatible string, relevant device tree changes, and their YAML bindings. --- In this series - PATCH 1: "dt-bindings: display/msm: Document MDSS on SA8775P" depends on dp binding documetion in this change: https://lore.kernel.org/all/20240923113150.24711-5-quic_mukhopad@quicinc.com/ - PATCH 5: "arm64: dts: qcom: sa8775p: add display dt nodes for MDSS0 and DPU" depends on the clock enablement change: https://lore.kernel.org/all/20240816-sa8775p-mm-v3-v1-0-77d53c3c0cef@quicinc.com/ --- [v4] - Removed new YAML added for sa8775p dpu dt-binding documention as it is similar to qcom,sm8650-dpu.yaml and added the compatible in same. [Krzysztof] [v3] -Edited copyright for catalog changes. [Dmitry] -Fix dt_binding_check tool errors(update reg address as address-cells and size-cells of root node one and maintain the same for child nodes of mdss, added additionalProperties in schema). [Rob, Bjorn, Krzysztof] -Add QCOM_ICC_TAG_ACTIVE_ONLY interconnect path tag to mdp0-mem and mdp1-mem path in devicetree. [Dmitry] -Update commit subject and message for DT change. [Dmitry] -Remove interconnect path tags from dt bindings. (ref sm8450-mdss yaml) [v2] - Updated cover letter subject and message. [Dmitry] - Use fake DISPCC nodes to avoid clock dependencies in dt-bindings. [Dmitry] - Update bindings by fixing dt_binding_check tool errors (update includes in example), adding proper spacing and indentation in the binding example, droping unused labels, droping status disable, adding reset node. [Dmitry, Rob, Krzysztof] - Reorder compatible string of MDSS and DPU based on alphabetical order.[Dmitry] - add reg_bus_bw in msm_mdss_data. [Dmitry] - Fix indentation in the devicetree. [Dmitry] -- 2.34.1 --- Mahadevan (5): dt-bindings: display/msm: Document MDSS on SA8775P dt-bindings: display/msm: Document the DPU for SA8775P drm/msm: mdss: Add SA8775P support drm/msm/dpu: Add SA8775P support arm64: dts: qcom: sa8775p: add display dt nodes for MDSS0 and DPU .../bindings/display/msm/qcom,sa8775p-mdss.yaml | 241 ++++++++++ .../bindings/display/msm/qcom,sm8650-dpu.yaml | 1 + arch/arm64/boot/dts/qcom/sa8775p.dtsi | 89 ++++ .../drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 485 +++++++++++++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + drivers/gpu/drm/msm/msm_mdss.c | 11 + 8 files changed, 830 insertions(+) --- base-commit: e390603cfa79c860ed35e073f5fe77805b067a8e change-id: 20240930-patchv3_1-600cbc1549e8 Best regards,