| Message ID | 20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org (mailing list archive) |
|---|---|
| Headers | show |
| Series | drm/msm/dpu: Support quad pipe with dual-DSI | expand |
On Wed, Oct 09, 2024 at 04:50:13PM GMT, Jun Nie wrote: > > --- > 2 or more SSPPs and dual-DSI interface are need for super wide DSI panel. > And 4 DSC are prefered for power optimal in this case. This patch set > extend number of pipes to 4 and revise related mixer blending logic > to support quad pipe. All these changes depends on the virtual plane > feature to split a super wide drm plane horizontally into 2 or more sub > clip. Thus DMA of multiple SSPPs can share the effort of fetching the > whole drm plane. > > The first pipe pair co-work with the first mixer pair to cover the left > half of screen and 2nd pair of pipes and mixers are for the right half > of screen. If a plane is only for the right half of screen, only one > or two of pipes in the 2nd pipe pair are valid, and no SSPP or mixer is > assinged for invalid pipe. > > For those panel that does not require quad-pipe, only 1 or 2 pipes in > the 1st pipe pair will be used. There is no concept of right half of > screen. > > For legacy non virtual plane mode, the first 1 or 2 pipes are used for > the single SSPP and its multi-rect mode. > > This patch set depends on virtual plane patch set v5 and flexible > number of DSC patch set: > https://patchwork.freedesktop.org/series/135456/ > > Changes in v2: > - Revise the patch sequence with changing to 2 pipes topology first. Then > prepare for quad-pipe setup, then enable quad-pipe at last. Is this the only change? Doesn't seem so. Please don't make it harder than it should be. > - Link to v1: https://lore.kernel.org/all/20240829-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-8-v1-0-bdb05b4b5a2e@linaro.org/ > > Signed-off-by: Jun Nie <jun.nie@linaro.org> > > --- > Jun Nie (14): > drm/msm/dpu: polish log for resource allocation > drm/msm/dpu: decide right side per last bit > drm/msm/dpu: fix mixer number counter on allocation > drm/msm/dpu: switch RM to use crtc_id rather than enc_id for allocation > drm/msm/dpu: handle pipes as array > drm/msm/dpu: split PIPES_PER_STAGE definition per plane and mixer > drm/msm/dpu: bind correct pingpong for quad pipe > drm/msm/dpu: update mixer number info earlier > drm/msm/dpu: blend pipes per mixer pairs config > drm/msm/dpu: Support quad-pipe in SSPP checking > drm/msm/dpu: Share SSPP info for multi-rect case > drm/msm/dpu: support plane splitting in quad-pipe case > drm/msm/dpu: support SSPP assignment for quad-pipe case > drm/msm/dpu: Enable quad-pipe for DSC and dual-DSI case > > drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 74 ++-- > drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 12 +- > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 69 ++-- > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 3 +- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 2 +- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 4 +- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 4 +- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 2 + > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 12 +- > drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 408 +++++++++++++---------- > drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 12 +- > drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 210 ++++++------ > drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 19 +- > drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 10 +- > 15 files changed, 478 insertions(+), 364 deletions(-) > --- > base-commit: eac5b436019c2eeb005f7bdf3ca29d5e8f443d67 > change-id: 20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-1142507692ba > > Best regards, > -- > Jun Nie <jun.nie@linaro.org> >
--- 2 or more SSPPs and dual-DSI interface are need for super wide DSI panel. And 4 DSC are prefered for power optimal in this case. This patch set extend number of pipes to 4 and revise related mixer blending logic to support quad pipe. All these changes depends on the virtual plane feature to split a super wide drm plane horizontally into 2 or more sub clip. Thus DMA of multiple SSPPs can share the effort of fetching the whole drm plane. The first pipe pair co-work with the first mixer pair to cover the left half of screen and 2nd pair of pipes and mixers are for the right half of screen. If a plane is only for the right half of screen, only one or two of pipes in the 2nd pipe pair are valid, and no SSPP or mixer is assinged for invalid pipe. For those panel that does not require quad-pipe, only 1 or 2 pipes in the 1st pipe pair will be used. There is no concept of right half of screen. For legacy non virtual plane mode, the first 1 or 2 pipes are used for the single SSPP and its multi-rect mode. This patch set depends on virtual plane patch set v5 and flexible number of DSC patch set: https://patchwork.freedesktop.org/series/135456/ Changes in v2: - Revise the patch sequence with changing to 2 pipes topology first. Then prepare for quad-pipe setup, then enable quad-pipe at last. - Link to v1: https://lore.kernel.org/all/20240829-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-8-v1-0-bdb05b4b5a2e@linaro.org/ Signed-off-by: Jun Nie <jun.nie@linaro.org> --- Jun Nie (14): drm/msm/dpu: polish log for resource allocation drm/msm/dpu: decide right side per last bit drm/msm/dpu: fix mixer number counter on allocation drm/msm/dpu: switch RM to use crtc_id rather than enc_id for allocation drm/msm/dpu: handle pipes as array drm/msm/dpu: split PIPES_PER_STAGE definition per plane and mixer drm/msm/dpu: bind correct pingpong for quad pipe drm/msm/dpu: update mixer number info earlier drm/msm/dpu: blend pipes per mixer pairs config drm/msm/dpu: Support quad-pipe in SSPP checking drm/msm/dpu: Share SSPP info for multi-rect case drm/msm/dpu: support plane splitting in quad-pipe case drm/msm/dpu: support SSPP assignment for quad-pipe case drm/msm/dpu: Enable quad-pipe for DSC and dual-DSI case drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 74 ++-- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 12 +- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 69 ++-- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 3 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 4 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 4 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 2 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 12 +- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 408 +++++++++++++---------- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 12 +- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 210 ++++++------ drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 19 +- drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 10 +- 15 files changed, 478 insertions(+), 364 deletions(-) --- base-commit: eac5b436019c2eeb005f7bdf3ca29d5e8f443d67 change-id: 20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-1142507692ba Best regards,