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Tue, 15 Oct 2024 14:17:11 GMT Received: from nsssdc-sh01-lnx.ap.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 15 Oct 2024 07:17:06 -0700 From: Luo Jie Subject: [PATCH v4 0/4] Add CMN PLL clock controller driver for IPQ9574 Date: Tue, 15 Oct 2024 22:16:50 +0800 Message-ID: <20241015-qcom_ipq_cmnpll-v4-0-27817fbe3505@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAFN5DmcC/2WNwQ6CMBBEf4Xs2ZptabB68j8MIbIssgkUaJVoC P9u5erxTWberBA5CEe4ZCsEXiTK6BPYQwbU3f2DlTSJwaCxGrVVM41DJdNc0eCnvld1w1jkrrV aF5BWU+BW3rvxVibuJD7H8NkPlvyX7i505vTnWnKFyjHimZjY1eY6v4TE0zEVody27QvG0YrOs AAAAA== To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , Konrad Dybcio CC: , , , , , , , , , , , , Luo Jie , Krzysztof Kozlowski X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; 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This driver configures the CMN PLL clock controller to enable the output clocks. The networking blocks include the internal blocks such as PPE (Packet Process Engine) and PCS blocks, and external hardware such as Ethernet PHY or switch. The CMN PLL block also outputs fixed rate clocks to GCC, such as 24 MHZ as XO clock and 32 KHZ as sleep clock supplied to GCC. The controller expects the input reference clock from the internal Wi-Fi block acting as the clock source. The output clocks supplied by the controller are fixed rate clocks. The CMN PLL hardware block does not include any other function other than enabling the clocks to the networking hardware blocks and GCC. The driver is being enabled to support IPQ9574 SoC initially, and will be extended for other SoCs. Signed-off-by: Luo Jie --- Changes in v4: - Rename driver file to ipq-cmn-pll.c - Register CMN PLL as a 12 GHZ clock. - Configure CMN PLL input ref clock using clk_ops::determine_rate(). Add the additional output clocks to GCC and PCS. - Update the same information in dtbindings. - Use PM clock APIs for input clock enablement. - Link to v3: https://lore.kernel.org/r/20240827-qcom_ipq_cmnpll-v3-0-8e009cece8b2@quicinc.com Changes in v3: - Update description of dt-binding to explain scope of 'CMN' in CMN PLL. - Collect Reviewed-by tags for dtbindings and defconfig patches. - Enable PLL_LOCKED check for the stability of output clocks. - Link to v2: https://lore.kernel.org/r/20240820-qcom_ipq_cmnpll-v2-0-b000dd335280@quicinc.com Changes in v2: - Rename the dt-binding file with the compatible. - Remove property 'clock-output-names' from dt-bindings and define names in the driver. Add qcom,ipq-cmn-pll.h to export the output clock specifier. - Alphanumeric ordering of 'cmn_pll_ref_clk' node in DTS. - Fix allmodconfig error reported by test robot. - Replace usage of "common" to "CMN" to match the name with the hardware specification. - Clarify in commit message on scope of CMN PLL function. - Link to v1: https://lore.kernel.org/r/20240808-qcom_ipq_cmnpll-v1-0-b0631dcbf785@quicinc.com --- Luo Jie (4): dt-bindings: clock: qcom: Add CMN PLL clock controller for IPQ SoC clk: qcom: Add CMN PLL clock controller driver for IPQ SoC arm64: defconfig: Enable Qualcomm IPQ CMN PLL clock controller arm64: dts: qcom: Add CMN PLL node for IPQ9574 SoC .../bindings/clock/qcom,ipq9574-cmn-pll.yaml | 85 +++++ arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi | 6 +- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 20 +- arch/arm64/configs/defconfig | 1 + drivers/clk/qcom/Kconfig | 10 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/ipq-cmn-pll.c | 411 +++++++++++++++++++++ include/dt-bindings/clock/qcom,ipq-cmn-pll.h | 22 ++ 8 files changed, 554 insertions(+), 2 deletions(-) --- base-commit: d61a00525464bfc5fe92c6ad713350988e492b88 change-id: 20241014-qcom_ipq_cmnpll-bde0638f4116 Best regards,