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Tue, 22 Oct 2024 11:53:01 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49MBr01c008773 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 22 Oct 2024 11:53:00 GMT Received: from hu-tdas-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 22 Oct 2024 04:52:56 -0700 From: Taniya Das <quic_tdas@quicinc.com> Subject: [PATCH v4 0/4] Add GCC and RPMH clock controller for QCS615 SoC Date: Tue, 22 Oct 2024 17:22:49 +0530 Message-ID: <20241022-qcs615-clock-driver-v4-0-3d716ad0d987@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: <linux-arm-msm.vger.kernel.org> List-Subscribe: <mailto:linux-arm-msm+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-arm-msm+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Type: text/plain; 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Add GCC and RPMH clock controller for QCS615 SoC
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On Tue, 22 Oct 2024 17:22:49 +0530, Taniya Das wrote: > Add support for Global clock controller(GCC) and the RPMH clock > controller for the Qualcomm QCS615 SoC. > > The QCS615 SoC is added as part of the below series. > https://lore.kernel.org/all/20240913-add_initial_support_for_qcs615-v2-0-9236223e7dab@quicinc.com/ > > Signed-off-by: Taniya Das <quic_tdas@quicinc.com> > > [...] Applied, thanks! [3/4] dt-bindings: clock: qcom: Add QCS615 GCC clocks commit: f4d3d7340e719dd3d2c23ce8d6c360e2f93ba7e4 Best regards,
Add support for Global clock controller(GCC) and the RPMH clock controller for the Qualcomm QCS615 SoC. The QCS615 SoC is added as part of the below series. https://lore.kernel.org/all/20240913-add_initial_support_for_qcs615-v2-0-9236223e7dab@quicinc.com/ Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Changes in v4: - Update the comment in the code where gpll0_out_aux2_div and gpll3_out_aux2_div are fixed divider clocks and not the PLL output clocks. [Dmitry] - Link to v3: https://lore.kernel.org/lkml/20241016-qcs615-clock-driver-v3-0-bb5d4135db45@quicinc.com Changes in v3: - Update the gcc_pcie_0_aux_clk_src to use clk_rcg2_shared_ops. [Dmitry] - Remove an extra line [Dmitry] - Link to v2: https://lore.kernel.org/lkml/20240920-qcs615-clock-driver-v2-0-2f6de44eb2aa@quicinc.com --- Changes in v2: - Update the compatible in alphabetical order for RPMHCC bindings and driver. - Remove the extra ":" from the GCC bindings. - Update the GCC Kconfig for some required configs and move the GCC init from module to subsys_initcall(). - Link to v1: https://lore.kernel.org/r/20240919-qcs615-clock-driver-v1-0-51c0cc92e3a2@quicinc.com --- Taniya Das (4): dt-bindings: clock: qcom-rpmhcc: Add RPMHCC bindings for QCS615 clk: qcom: rpmhcc: Add support for QCS615 Clocks dt-bindings: clock: qcom: Add QCS615 GCC clocks clk: qcom: gcc: Add support for QCS615 GCC clocks .../devicetree/bindings/clock/qcom,qcs615-gcc.yaml | 59 + .../devicetree/bindings/clock/qcom,rpmhcc.yaml | 1 + drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clk-rpmh.c | 19 + drivers/clk/qcom/gcc-qcs615.c | 3034 ++++++++++++++++++++ include/dt-bindings/clock/qcom,qcs615-gcc.h | 211 ++ 7 files changed, 3334 insertions(+) --- base-commit: 55bcd2e0d04c1171d382badef1def1fd04ef66c5 change-id: 20240919-qcs615-clock-driver-d74abed69854 Best regards,