mbox series

[v3,0/3] soc: qcom: llcc: Add LLCC support for the QCS8300 platform

Message ID 20241031-qcs8300_llcc-v3-0-bb56952cb83b@quicinc.com (mailing list archive)
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Series soc: qcom: llcc: Add LLCC support for the QCS8300 platform | expand

Message

Jingyi Wang Oct. 31, 2024, 7:14 a.m. UTC
The QCS8300 platform has LLCC(Last Level Cache Controller) as the system
cache controller. Add binding, configuration and device tree node to
support this. There is an errata to get the number of the banks of the
LLCC on QCS8300 platform, hardcode it as a workaround.

This series depends on below patch series:
https://lore.kernel.org/all/20240925-qcs8300_initial_dtsi-v2-0-494c40fa2a42@quicinc.com/ - Reviewed
https://lore.kernel.org/all/20241026-sar2130p-llcc-v3-0-2a58fa1b4d12@linaro.org/ - Reviewed

Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>
---
Changes in v3:
- patch rebased for using "num_banks" property defined in the config for hardcoding
- Add reviewed-by tag for dt change
- Link to v2: https://lore.kernel.org/r/20241010-qcs8300_llcc-v2-0-d4123a241db2@quicinc.com

Changes in v2:
- Hardcoding instead of adding property in dt node and remove related patches
- Add LLCC deivcetree node
- Add reviewed-by tag for binding change
- Patch rebased for LLCC configuration format change
- Link to v1: https://lore.kernel.org/r/20240903-qcs8300_llcc_driver-v1-0-228659bdf067@quicinc.com

---
Jingyi Wang (3):
      dt-bindings: cache: qcom,llcc: Document the QCS8300 LLCC
      soc: qcom: llcc: Add LLCC configuration for the QCS8300 platform
      arm64: dts: qcom: qcs8300: Add LLCC support for QCS8300

 .../devicetree/bindings/cache/qcom,llcc.yaml       |  2 +
 arch/arm64/boot/dts/qcom/qcs8300.dtsi              | 15 +++++
 drivers/soc/qcom/llcc-qcom.c                       | 67 ++++++++++++++++++++++
 3 files changed, 84 insertions(+)
---
base-commit: dec9255a128e19c5fcc3bdb18175d78094cc624d
change-id: 20241031-qcs8300_llcc-32ab1ce4eeac
prerequisite-message-id: <20240925-qcs8300_initial_dtsi-v2-0-494c40fa2a42@quicinc.com>
prerequisite-patch-id: dc633d5aaac790776a8a213ea2faa4890a3f665d
prerequisite-patch-id: 9ecf4cb8b5842ac64e51d6baa0e6c1fbe449ee66
prerequisite-patch-id: 5a01283c8654ae7c696d9c69cb21505b71c5ca27
prerequisite-patch-id: 73c78f31fa1d504124d4a82b578a6a14126cccd8
prerequisite-message-id: <20241026-sar2130p-llcc-v3-0-2a58fa1b4d12@linaro.org>
prerequisite-patch-id: cdb161d351ba3ff4f9e53efaa67eb32b603af435
prerequisite-patch-id: dc04e235391820e4ab04c72ac64fd852e73fade5
prerequisite-patch-id: 6ca6eacd9ceca6d060d23ef95594fb892e51a506

Best regards,

Comments

Bjorn Andersson Nov. 4, 2024, 4:13 a.m. UTC | #1
On Thu, 31 Oct 2024 15:14:35 +0800, Jingyi Wang wrote:
> The QCS8300 platform has LLCC(Last Level Cache Controller) as the system
> cache controller. Add binding, configuration and device tree node to
> support this. There is an errata to get the number of the banks of the
> LLCC on QCS8300 platform, hardcode it as a workaround.
> 
> This series depends on below patch series:
> https://lore.kernel.org/all/20240925-qcs8300_initial_dtsi-v2-0-494c40fa2a42@quicinc.com/ - Reviewed
> https://lore.kernel.org/all/20241026-sar2130p-llcc-v3-0-2a58fa1b4d12@linaro.org/ - Reviewed
> 
> [...]

Applied, thanks!

[1/3] dt-bindings: cache: qcom,llcc: Document the QCS8300 LLCC
      commit: a83e18ca83583ce191848ee73975894d43093cde
[2/3] soc: qcom: llcc: Add LLCC configuration for the QCS8300 platform
      commit: 584e936feedfcf678510a749f407115bdc811fbd

Best regards,