| Message ID | 20241106221341.2218416-1-quic_mrana@quicinc.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Add Qualcomm SA8255p based firmware managed PCIe root complex | expand |
On Wed, Nov 06, 2024 at 02:13:37PM -0800, Mayank Rana wrote: > Based on received feedback, this patch series adds support with existing > Linux qcom-pcie.c driver to get PCIe host root complex functionality on > Qualcomm SA8255P auto platform. > > 1. Interface to allow requesting firmware to manage system resources and > performing PCIe Link up (devicetree binding in terms of power domain and > runtime PM APIs is used in driver) > > 2. SA8255P is using Synopsys Designware PCIe controller which supports MSI > controller. Using existing MSI controller based functionality by exporting > important pcie dwc core driver based MSI APIs, and using those from > pcie-qcom.c driver. > > Below architecture is used on Qualcomm SA8255P auto platform to get ECAM > compliant PCIe controller based functionality. Here firmware VM based PCIe > driver takes care of resource management and performing PCIe link related > handling (D0 and D3cold). Linux pcie-qcom.c driver uses power domain to > request firmware VM to perform these operations using SCMI interface. > -------------------- > > > ┌────────────────────────┐ > │ │ > ┌──────────────────────┐ │ SHARED MEMORY │ ┌──────────────────────────┐ > │ Firmware VM │ │ │ │ Linux VM │ > │ ┌─────────┐ │ │ │ │ ┌────────────────┐ │ > │ │ Drivers │ ┌──────┐ │ │ │ │ │ PCIE Qcom │ │ > │ │ PCIE PHY◄─┤ │ │ │ ┌────────────────┐ │ │ │ driver │ │ > │ │ │ │ SCMI │ │ │ │ │ │ │ │ │ │ > │ │PCIE CTL │ │ │ ├─────────┼───► PCIE ◄───┼─────┐ │ └──┬──────────▲──┘ │ > │ │ ├─►Server│ │ │ │ SHMEM │ │ │ │ │ │ │ > │ │Clk, Vreg│ │ │ │ │ │ │ │ │ │ ┌──▼──────────┴──┐ │ > │ │GPIO,GDSC│ └─▲──┬─┘ │ │ └────────────────┘ │ └──────┼────┤PCIE SCMI Inst │ │ > │ └─────────┘ │ │ │ │ │ │ └──▲──────────┬──┘ │ > │ │ │ │ │ │ │ │ │ │ > └───────────────┼──┼───┘ │ │ └───────┼──────────┼───────┘ > │ │ │ │ │ │ > │ │ └────────────────────────┘ │ │ > │ │ │ │ > │ │ │ │ > │ │ │ │ > │ │ │IRQ │HVC > IRQ │ │HVC │ │ > │ │ │ │ > │ │ │ │ > │ │ │ │ > ┌─────────────────┴──▼───────────────────────────────────────────────────────────┴──────────▼──────────────┐ > │ │ > │ │ > │ HYPERVISOR │ > │ │ > │ │ > │ │ > └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ > > ┌─────────────┐ ┌─────────────┐ ┌──────────┐ ┌───────────┐ ┌─────────────┐ ┌────────────┐ > │ │ │ │ │ │ │ │ │ PCIE │ │ PCIE │ > │ CLOCK │ │ REGULATOR │ │ GPIO │ │ GDSC │ │ PHY │ │ controller │ > └─────────────┘ └─────────────┘ └──────────┘ └───────────┘ └─────────────┘ └────────────┘ > Thanks a lot for working on this Mayank! This version looks good to me. I've left some comments, nothing alarming though. But I do want to hold up this series until we finalize the SCMI based design. - Mani > ---------- > Changes in V3: > - Drop usage of PCIE host generic driver usage, and splitting of MSI functionality > - Modified existing pcie-qcom.c driver to add support for getting ECAM compliant and firmware managed > PCIe root complex functionality > Link to v2: https://lore.kernel.org/linux-arm-kernel/925d1eca-975f-4eec-bdf8-ca07a892361a@quicinc.com/T/ > > Changes in V2: > - Drop new PCIe Qcom ECAM driver, and use existing PCIe designware based MSI functionality > - Add power domain based functionality within existing ECAM driver > Link to v1: https://lore.kernel.org/all/d10199df-5fb3-407b-b404-a0a4d067341f@quicinc.com/T/ > > Tested: > - Validated NVME functionality with PCIe0 on SA8255P-RIDE platform > > Mayank Rana (3): > PCI: dwc: Export dwc MSI controller related APIs > PCI: qcom: Add firmware managed ECAM compliant PCIe root complex > functionality > dt-bindings: PCI: qcom,pcie-sa8255p: Document ECAM compliant PCIe root > complex > > .../devicetree/bindings/pci/qcom,pcie-sa8255p.yaml | 100 +++++++++++++++++++++ > drivers/pci/controller/dwc/Kconfig | 1 + > drivers/pci/controller/dwc/pcie-designware-host.c | 38 ++++---- > drivers/pci/controller/dwc/pcie-designware.h | 14 +++ > drivers/pci/controller/dwc/pcie-qcom.c | 69 ++++++++++++-- > 5 files changed, 199 insertions(+), 23 deletions(-) > create mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie-sa8255p.yaml > > -- > 2.7.4 >
On 11/15/2024 3:28 AM, Manivannan Sadhasivam wrote: > On Wed, Nov 06, 2024 at 02:13:37PM -0800, Mayank Rana wrote: >> Based on received feedback, this patch series adds support with existing >> Linux qcom-pcie.c driver to get PCIe host root complex functionality on >> Qualcomm SA8255P auto platform. >> >> 1. Interface to allow requesting firmware to manage system resources and >> performing PCIe Link up (devicetree binding in terms of power domain and >> runtime PM APIs is used in driver) >> >> 2. SA8255P is using Synopsys Designware PCIe controller which supports MSI >> controller. Using existing MSI controller based functionality by exporting >> important pcie dwc core driver based MSI APIs, and using those from >> pcie-qcom.c driver. >> >> Below architecture is used on Qualcomm SA8255P auto platform to get ECAM >> compliant PCIe controller based functionality. Here firmware VM based PCIe >> driver takes care of resource management and performing PCIe link related >> handling (D0 and D3cold). Linux pcie-qcom.c driver uses power domain to >> request firmware VM to perform these operations using SCMI interface. >> -------------------- >> >> >> ┌────────────────────────┐ >> │ │ >> ┌──────────────────────┐ │ SHARED MEMORY │ ┌──────────────────────────┐ >> │ Firmware VM │ │ │ │ Linux VM │ >> │ ┌─────────┐ │ │ │ │ ┌────────────────┐ │ >> │ │ Drivers │ ┌──────┐ │ │ │ │ │ PCIE Qcom │ │ >> │ │ PCIE PHY◄─┤ │ │ │ ┌────────────────┐ │ │ │ driver │ │ >> │ │ │ │ SCMI │ │ │ │ │ │ │ │ │ │ >> │ │PCIE CTL │ │ │ ├─────────┼───► PCIE ◄───┼─────┐ │ └──┬──────────▲──┘ │ >> │ │ ├─►Server│ │ │ │ SHMEM │ │ │ │ │ │ │ >> │ │Clk, Vreg│ │ │ │ │ │ │ │ │ │ ┌──▼──────────┴──┐ │ >> │ │GPIO,GDSC│ └─▲──┬─┘ │ │ └────────────────┘ │ └──────┼────┤PCIE SCMI Inst │ │ >> │ └─────────┘ │ │ │ │ │ │ └──▲──────────┬──┘ │ >> │ │ │ │ │ │ │ │ │ │ >> └───────────────┼──┼───┘ │ │ └───────┼──────────┼───────┘ >> │ │ │ │ │ │ >> │ │ └────────────────────────┘ │ │ >> │ │ │ │ >> │ │ │ │ >> │ │ │ │ >> │ │ │IRQ │HVC >> IRQ │ │HVC │ │ >> │ │ │ │ >> │ │ │ │ >> │ │ │ │ >> ┌─────────────────┴──▼───────────────────────────────────────────────────────────┴──────────▼──────────────┐ >> │ │ >> │ │ >> │ HYPERVISOR │ >> │ │ >> │ │ >> │ │ >> └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ >> >> ┌─────────────┐ ┌─────────────┐ ┌──────────┐ ┌───────────┐ ┌─────────────┐ ┌────────────┐ >> │ │ │ │ │ │ │ │ │ PCIE │ │ PCIE │ >> │ CLOCK │ │ REGULATOR │ │ GPIO │ │ GDSC │ │ PHY │ │ controller │ >> └─────────────┘ └─────────────┘ └──────────┘ └───────────┘ └─────────────┘ └────────────┘ >> > > Thanks a lot for working on this Mayank! This version looks good to me. I've > left some comments, nothing alarming though. Thanks for reviewing change. I would address those in next patchset. > But I do want to hold up this series until we finalize the SCMI based design. ok. I want to send these changes which are prepared based on previously provided feedback, to see if we have any major concern here in terms of getting functionality. Regards, Mayank > - Mani > >> ---------- >> Changes in V3: >> - Drop usage of PCIE host generic driver usage, and splitting of MSI functionality >> - Modified existing pcie-qcom.c driver to add support for getting ECAM compliant and firmware managed >> PCIe root complex functionality >> Link to v2: https://lore.kernel.org/linux-arm-kernel/925d1eca-975f-4eec-bdf8-ca07a892361a@quicinc.com/T/ >> >> Changes in V2: >> - Drop new PCIe Qcom ECAM driver, and use existing PCIe designware based MSI functionality >> - Add power domain based functionality within existing ECAM driver >> Link to v1: https://lore.kernel.org/all/d10199df-5fb3-407b-b404-a0a4d067341f@quicinc.com/T/ >> >> Tested: >> - Validated NVME functionality with PCIe0 on SA8255P-RIDE platform >> >> Mayank Rana (3): >> PCI: dwc: Export dwc MSI controller related APIs >> PCI: qcom: Add firmware managed ECAM compliant PCIe root complex >> functionality >> dt-bindings: PCI: qcom,pcie-sa8255p: Document ECAM compliant PCIe root >> complex >> >> .../devicetree/bindings/pci/qcom,pcie-sa8255p.yaml | 100 +++++++++++++++++++++ >> drivers/pci/controller/dwc/Kconfig | 1 + >> drivers/pci/controller/dwc/pcie-designware-host.c | 38 ++++---- >> drivers/pci/controller/dwc/pcie-designware.h | 14 +++ >> drivers/pci/controller/dwc/pcie-qcom.c | 69 ++++++++++++-- >> 5 files changed, 199 insertions(+), 23 deletions(-) >> create mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie-sa8255p.yaml >> >> -- >> 2.7.4 >> >
On Fri, Nov 15, 2024 at 10:31:17AM -0800, Mayank Rana wrote: > > > On 11/15/2024 3:28 AM, Manivannan Sadhasivam wrote: > > On Wed, Nov 06, 2024 at 02:13:37PM -0800, Mayank Rana wrote: > > > Based on received feedback, this patch series adds support with existing > > > Linux qcom-pcie.c driver to get PCIe host root complex functionality on > > > Qualcomm SA8255P auto platform. > > > > > > 1. Interface to allow requesting firmware to manage system resources and > > > performing PCIe Link up (devicetree binding in terms of power domain and > > > runtime PM APIs is used in driver) > > > > > > 2. SA8255P is using Synopsys Designware PCIe controller which supports MSI > > > controller. Using existing MSI controller based functionality by exporting > > > important pcie dwc core driver based MSI APIs, and using those from > > > pcie-qcom.c driver. > > > > > > Below architecture is used on Qualcomm SA8255P auto platform to get ECAM > > > compliant PCIe controller based functionality. Here firmware VM based PCIe > > > driver takes care of resource management and performing PCIe link related > > > handling (D0 and D3cold). Linux pcie-qcom.c driver uses power domain to > > > request firmware VM to perform these operations using SCMI interface. > > > -------------------- > > > > > > > > > ┌────────────────────────┐ > > > │ │ > > > ┌──────────────────────┐ │ SHARED MEMORY │ ┌──────────────────────────┐ > > > │ Firmware VM │ │ │ │ Linux VM │ > > > │ ┌─────────┐ │ │ │ │ ┌────────────────┐ │ > > > │ │ Drivers │ ┌──────┐ │ │ │ │ │ PCIE Qcom │ │ > > > │ │ PCIE PHY◄─┤ │ │ │ ┌────────────────┐ │ │ │ driver │ │ > > > │ │ │ │ SCMI │ │ │ │ │ │ │ │ │ │ > > > │ │PCIE CTL │ │ │ ├─────────┼───► PCIE ◄───┼─────┐ │ └──┬──────────▲──┘ │ > > > │ │ ├─►Server│ │ │ │ SHMEM │ │ │ │ │ │ │ > > > │ │Clk, Vreg│ │ │ │ │ │ │ │ │ │ ┌──▼──────────┴──┐ │ > > > │ │GPIO,GDSC│ └─▲──┬─┘ │ │ └────────────────┘ │ └──────┼────┤PCIE SCMI Inst │ │ > > > │ └─────────┘ │ │ │ │ │ │ └──▲──────────┬──┘ │ > > > │ │ │ │ │ │ │ │ │ │ > > > └───────────────┼──┼───┘ │ │ └───────┼──────────┼───────┘ > > > │ │ │ │ │ │ > > > │ │ └────────────────────────┘ │ │ > > > │ │ │ │ > > > │ │ │ │ > > > │ │ │ │ > > > │ │ │IRQ │HVC > > > IRQ │ │HVC │ │ > > > │ │ │ │ > > > │ │ │ │ > > > │ │ │ │ > > > ┌─────────────────┴──▼───────────────────────────────────────────────────────────┴──────────▼──────────────┐ > > > │ │ > > > │ │ > > > │ HYPERVISOR │ > > > │ │ > > > │ │ > > > │ │ > > > └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ > > > ┌─────────────┐ ┌─────────────┐ ┌──────────┐ ┌───────────┐ ┌─────────────┐ ┌────────────┐ > > > │ │ │ │ │ │ │ │ │ PCIE │ │ PCIE │ > > > │ CLOCK │ │ REGULATOR │ │ GPIO │ │ GDSC │ │ PHY │ │ controller │ > > > └─────────────┘ └─────────────┘ └──────────┘ └───────────┘ └─────────────┘ └────────────┘ > > > > Thanks a lot for working on this Mayank! This version looks good to me. I've > > left some comments, nothing alarming though. > Thanks for reviewing change. I would address those in next patchset. > > > But I do want to hold up this series until we finalize the SCMI based design. > ok. I want to send these changes which are prepared based on previously > provided feedback, to see if we have any major concern here in terms of > getting functionality. > That's fine. My comment was a note to the maintainers. - Mani
Based on received feedback, this patch series adds support with existing Linux qcom-pcie.c driver to get PCIe host root complex functionality on Qualcomm SA8255P auto platform. 1. Interface to allow requesting firmware to manage system resources and performing PCIe Link up (devicetree binding in terms of power domain and runtime PM APIs is used in driver) 2. SA8255P is using Synopsys Designware PCIe controller which supports MSI controller. Using existing MSI controller based functionality by exporting important pcie dwc core driver based MSI APIs, and using those from pcie-qcom.c driver. Below architecture is used on Qualcomm SA8255P auto platform to get ECAM compliant PCIe controller based functionality. Here firmware VM based PCIe driver takes care of resource management and performing PCIe link related handling (D0 and D3cold). Linux pcie-qcom.c driver uses power domain to request firmware VM to perform these operations using SCMI interface. -------------------- ┌────────────────────────┐ │ │ ┌──────────────────────┐ │ SHARED MEMORY │ ┌──────────────────────────┐ │ Firmware VM │ │ │ │ Linux VM │ │ ┌─────────┐ │ │ │ │ ┌────────────────┐ │ │ │ Drivers │ ┌──────┐ │ │ │ │ │ PCIE Qcom │ │ │ │ PCIE PHY◄─┤ │ │ │ ┌────────────────┐ │ │ │ driver │ │ │ │ │ │ SCMI │ │ │ │ │ │ │ │ │ │ │ │PCIE CTL │ │ │ ├─────────┼───► PCIE ◄───┼─────┐ │ └──┬──────────▲──┘ │ │ │ ├─►Server│ │ │ │ SHMEM │ │ │ │ │ │ │ │ │Clk, Vreg│ │ │ │ │ │ │ │ │ │ ┌──▼──────────┴──┐ │ │ │GPIO,GDSC│ └─▲──┬─┘ │ │ └────────────────┘ │ └──────┼────┤PCIE SCMI Inst │ │ │ └─────────┘ │ │ │ │ │ │ └──▲──────────┬──┘ │ │ │ │ │ │ │ │ │ │ │ └───────────────┼──┼───┘ │ │ └───────┼──────────┼───────┘ │ │ │ │ │ │ │ │ └────────────────────────┘ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │IRQ │HVC IRQ │ │HVC │ │ │ │ │ │ │ │ │ │ │ │ │ │ ┌─────────────────┴──▼───────────────────────────────────────────────────────────┴──────────▼──────────────┐ │ │ │ │ │ HYPERVISOR │ │ │ │ │ │ │ └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ ┌─────────────┐ ┌─────────────┐ ┌──────────┐ ┌───────────┐ ┌─────────────┐ ┌────────────┐ │ │ │ │ │ │ │ │ │ PCIE │ │ PCIE │ │ CLOCK │ │ REGULATOR │ │ GPIO │ │ GDSC │ │ PHY │ │ controller │ └─────────────┘ └─────────────┘ └──────────┘ └───────────┘ └─────────────┘ └────────────┘ ---------- Changes in V3: - Drop usage of PCIE host generic driver usage, and splitting of MSI functionality - Modified existing pcie-qcom.c driver to add support for getting ECAM compliant and firmware managed PCIe root complex functionality Link to v2: https://lore.kernel.org/linux-arm-kernel/925d1eca-975f-4eec-bdf8-ca07a892361a@quicinc.com/T/ Changes in V2: - Drop new PCIe Qcom ECAM driver, and use existing PCIe designware based MSI functionality - Add power domain based functionality within existing ECAM driver Link to v1: https://lore.kernel.org/all/d10199df-5fb3-407b-b404-a0a4d067341f@quicinc.com/T/ Tested: - Validated NVME functionality with PCIe0 on SA8255P-RIDE platform Mayank Rana (3): PCI: dwc: Export dwc MSI controller related APIs PCI: qcom: Add firmware managed ECAM compliant PCIe root complex functionality dt-bindings: PCI: qcom,pcie-sa8255p: Document ECAM compliant PCIe root complex .../devicetree/bindings/pci/qcom,pcie-sa8255p.yaml | 100 +++++++++++++++++++++ drivers/pci/controller/dwc/Kconfig | 1 + drivers/pci/controller/dwc/pcie-designware-host.c | 38 ++++---- drivers/pci/controller/dwc/pcie-designware.h | 14 +++ drivers/pci/controller/dwc/pcie-qcom.c | 69 ++++++++++++-- 5 files changed, 199 insertions(+), 23 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie-sa8255p.yaml