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Tue, 17 Dec 2024 10:10:21 +0000 Received: from APTAIPPMTA02.qualcomm.com (APTAIPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 4BHAALOR016467; Tue, 17 Dec 2024 10:10:21 GMT Received: from cse-cd02-lnx.ap.qualcomm.com (cse-cd02-lnx.qualcomm.com [10.64.75.246]) by APTAIPPMTA02.qualcomm.com (PPS) with ESMTPS id 4BHAALbC016465 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 17 Dec 2024 10:10:21 +0000 Received: by cse-cd02-lnx.ap.qualcomm.com (Postfix, from userid 4571896) id 26F171BD7; Tue, 17 Dec 2024 18:10:19 +0800 (CST) From: Yuanjie Yang To: ulf.hansson@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, bhupesh.sharma@linaro.org, andersson@kernel.org, konradybcio@kernel.org Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, quic_tingweiz@quicinc.com, quic_yuanjiey@quicinc.com Subject: [PATCH v5 0/2] Enable SDHC1 and SDHC2 on QCS615 Date: Tue, 17 Dec 2024 18:10:15 +0800 Message-Id: <20241217101017.2933587-1-quic_yuanjiey@quicinc.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: ZrAmx5clM0LPcLlKgrlvpYB89jDQNhQ0 X-Proofpoint-GUID: ZrAmx5clM0LPcLlKgrlvpYB89jDQNhQ0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 clxscore=1015 lowpriorityscore=0 suspectscore=0 priorityscore=1501 malwarescore=0 impostorscore=0 mlxscore=0 mlxlogscore=999 phishscore=0 spamscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412170083 Add SDHC1 and SDHC2 support to the QCS615 Ride platform. The SDHC1 and SDHC2 of QCS615 are derived from SM6115. Include the configuration of SDHC1-related and SDHC2-related opp, power, and interconnect settings in the device tree. Signed-off-by: Yuanjie Yang --- This patch series depends on below patch series: - gcc: https://lore.kernel.org/all/20241022-qcs615-clock-driver-v4-0-3d716ad0d987@quicinc.com/ Changes in v5: - Modify SDHC1 and SDHC2 interconnects, for the cpu path, use QCOM_ICC_TAG_ACTIVE_ONLY to replace QCOM_ICC_TAG_ALWAYS - For SDHC1 and SDHC2, Add a newline before status - Rebase Change on tag: next-20241217 - Modify dependency changes - Link to v4: https://lore.kernel.org/all/20241206023711.2541716-1-quic_yuanjiey@quicinc.com/ Changes in v4: - Move properties which are not properties of the SoC to board DTS - Add ice region to SDHC1 Node reg - Add 50Mhz 200Mhz to SDHC1 opp table, add 50Mhz to SDHC2 opp table - fix SDHC2 Node compatible space - Link to v3: https://lore.kernel.org/all/20241122065101.1918470-1-quic_yuanjiey@quicinc.com/ Changes in v3: - Improve the commit messages and cover letter - Link to v2: https://lore.kernel.org/all/20241106072343.2070933-1-quic_yuanjiey@quicinc.com/ Changes in v2: - Improve the commit messages and cover letter - Remove applied patches 1 - Pad sdhc_1 node and sdhc_2 node register addresses to 8 hex digits - Adjust sdhc_1 node and sdhc_2 node register addresses to hexadecimal - Modify sdhc_2 vqmmc-supply incorrect power configuration - Link to v1: https://lore.kernel.org/all/20241023092708.604195-1-quic_yuanjiey@quicinc.com/ --- Yuanjie Yang (2): arm64: dts: qcom: qcs615: add SDHC1 and SDHC2 arm64: dts: qcom: qcs615-ride: enable SDHC1 and SDHC2 arch/arm64/boot/dts/qcom/qcs615-ride.dts | 37 ++++ arch/arm64/boot/dts/qcom/qcs615.dtsi | 211 +++++++++++++++++++++++ 2 files changed, 248 insertions(+)