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Wed, 18 Dec 2024 10:40:19 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4BIAeI6l021197 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 18 Dec 2024 10:40:18 GMT Received: from lijuang2-gv.ap.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 18 Dec 2024 02:40:12 -0800 From: Lijuan Gao <quic_lijuang@quicinc.com> Subject: [PATCH 0/2] arm64: qcom: Add BWMON support for QCS615 Date: Wed, 18 Dec 2024 18:39:37 +0800 Message-ID: <20241218-add_bwmon_support_for_qcs615-v1-0-680d798a19e5@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: <linux-arm-msm.vger.kernel.org> List-Subscribe: <mailto:linux-arm-msm+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-arm-msm+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Type: text/plain; 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arm64: qcom: Add BWMON support for QCS615
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Document and add CPU and LLCC BWMON nodes and their corresponding OPP tables for QCS615 SoC. The patch has undergone the following verifications: - Successfully passed dt_binding_check with DT_CHECKER_FLAGS=-m for binding file - Successfully passed dtbs_check with W=1 for dts - Verified each item in the CPU and LLCC OPP tables, and the BCM threshold and clock values meet expectations. Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com> --- Lijuan Gao (2): dt-bindings: interconnect: qcom-bwmon: Document QCS615 bwmon compatibles arm64: dts: qcom: qcs615: Add CPU and LLCC BWMON support .../bindings/interconnect/qcom,msm8998-bwmon.yaml | 2 + arch/arm64/boot/dts/qcom/qcs615.dtsi | 72 ++++++++++++++++++++++ 2 files changed, 74 insertions(+) --- base-commit: fdb298fa865b0136f7be842e6c2e6310dede421a change-id: 20241217-add_bwmon_support_for_qcs615-a8c7a4034379 Best regards,