| Message ID | 20250113-support-pll-reconfigure-v1-0-1fae6bc1062d@quicinc.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Add support to reconfigure PLL | expand |
Hello Taniya, On Mon, 13 Jan 2025 at 18:27, Taniya Das <quic_tdas@quicinc.com> wrote: > > During boot-up, there is a possibility that the PLL configuration might > be missed even after invoking pll_configure() from the clock controller > probe. This is often due to the PLL being connected to rail or rails > that are in an OFF state and current clock controller also cannot vote > on multiple rails. As a result, the PLL may be enabled with suboptimal > settings, leading to functional issues. > > The PLL configuration, now part of clk_alpha_pll, can be reused to > reconfigure the PLL to a known good state before scaling for frequency. > The 'clk_alpha_pll_reconfigure()' can be updated to support more PLLs > in future. > > The IRIS driver support added > https://lore.kernel.org/all/20241212-qcom-video-iris-v9-0-e8c2c6bd4041@quicinc.com/ > observes the pll latch warning during boot up due to the dependency of > the PLL not in good state, thus add config support for SM8550 Video > clock controller PLLs. > > Signed-off-by: Taniya Das <quic_tdas@quicinc.com> > --- > Taniya Das (3): > clk: qcom: clk-alpha-pll: Integrate PLL configuration into PLL structure > clk: qcom: clk-alpha-pll: Add support to reconfigure PLL > clk: qcom: videocc-sm8550: Update the pll config for Video PLLs > > drivers/clk/qcom/clk-alpha-pll.c | 30 ++++++++++++++++++++++++++++++ > drivers/clk/qcom/clk-alpha-pll.h | 2 ++ > drivers/clk/qcom/videocc-sm8550.c | 2 ++ > 3 files changed, 34 insertions(+) > --- > base-commit: 37136bf5c3a6f6b686d74f41837a6406bec6b7bc > change-id: 20250113-support-pll-reconfigure-9a9cbb43a90b I tested the full patchset on my X Elite Dell XPS and can confirm that the Lucid PLL latch failed warning is gone when using the iris driver. Tested-by: Stefan Schmidt <stefan.schmidt@linaro.org> # x1e80100 (Dell XPS 13 9345) regards Stefan Schmidt
On Mon, Jan 13, 2025 at 10:57:03PM +0530, Taniya Das wrote: > During boot-up, there is a possibility that the PLL configuration might > be missed even after invoking pll_configure() from the clock controller > probe. This is often due to the PLL being connected to rail or rails > that are in an OFF state and current clock controller also cannot vote > on multiple rails. As a result, the PLL may be enabled with suboptimal > settings, leading to functional issues. > > The PLL configuration, now part of clk_alpha_pll, can be reused to > reconfigure the PLL to a known good state before scaling for frequency. > The 'clk_alpha_pll_reconfigure()' can be updated to support more PLLs > in future. This sounds like a hack. You already describe the underlying problem (and indirectly its solution) in the first paragraph above, namely that the video clock controller has not enabled the power domain needed to configure the PLL. I believe support for clock controllers that need to enable multiple power domains is on its way into 6.15: https://lore.kernel.org/lkml/20250117-b4-linux-next-24-11-18-clock-multiple-power-domains-v10-0-13f2bb656dad@linaro.org/ Perhaps that's what you need to fix this properly. > The IRIS driver support added > https://lore.kernel.org/all/20241212-qcom-video-iris-v9-0-e8c2c6bd4041@quicinc.com/ > observes the pll latch warning during boot up due to the dependency of > the PLL not in good state, thus add config support for SM8550 Video > clock controller PLLs. > Taniya Das (3): > clk: qcom: clk-alpha-pll: Integrate PLL configuration into PLL structure > clk: qcom: clk-alpha-pll: Add support to reconfigure PLL > clk: qcom: videocc-sm8550: Update the pll config for Video PLLs Johan
On 2/4/2025 3:38 PM, Johan Hovold wrote: > On Mon, Jan 13, 2025 at 10:57:03PM +0530, Taniya Das wrote: >> During boot-up, there is a possibility that the PLL configuration might >> be missed even after invoking pll_configure() from the clock controller >> probe. This is often due to the PLL being connected to rail or rails >> that are in an OFF state and current clock controller also cannot vote >> on multiple rails. As a result, the PLL may be enabled with suboptimal >> settings, leading to functional issues. >> >> The PLL configuration, now part of clk_alpha_pll, can be reused to >> reconfigure the PLL to a known good state before scaling for frequency. >> The 'clk_alpha_pll_reconfigure()' can be updated to support more PLLs >> in future. > > This sounds like a hack. You already describe the underlying problem (and > indirectly its solution) in the first paragraph above, namely that the > video clock controller has not enabled the power domain needed to > configure the PLL. > This is not a hack, but another alternative way to ensure the PLL is configured to the right configuration before being used. > I believe support for clock controllers that need to enable multiple > power domains is on its way into 6.15: > > https://lore.kernel.org/lkml/20250117-b4-linux-next-24-11-18-clock-multiple-power-domains-v10-0-13f2bb656dad@linaro.org/ > > Perhaps that's what you need to fix this properly. > Yes, this is just to add a dependency on clock controller to put the rail vote, but this series does not fully solve the clock controller's PLL requirement problems. >> The IRIS driver support added >> https://lore.kernel.org/all/20241212-qcom-video-iris-v9-0-e8c2c6bd4041@quicinc.com/ >> observes the pll latch warning during boot up due to the dependency of >> the PLL not in good state, thus add config support for SM8550 Video >> clock controller PLLs. > >> Taniya Das (3): >> clk: qcom: clk-alpha-pll: Integrate PLL configuration into PLL structure >> clk: qcom: clk-alpha-pll: Add support to reconfigure PLL >> clk: qcom: videocc-sm8550: Update the pll config for Video PLLs > > Johan
On Tue, Feb 04, 2025 at 11:13:08PM +0530, Taniya Das wrote: > On 2/4/2025 3:38 PM, Johan Hovold wrote: > > On Mon, Jan 13, 2025 at 10:57:03PM +0530, Taniya Das wrote: > >> During boot-up, there is a possibility that the PLL configuration might > >> be missed even after invoking pll_configure() from the clock controller > >> probe. This is often due to the PLL being connected to rail or rails > >> that are in an OFF state and current clock controller also cannot vote > >> on multiple rails. As a result, the PLL may be enabled with suboptimal > >> settings, leading to functional issues. > >> > >> The PLL configuration, now part of clk_alpha_pll, can be reused to > >> reconfigure the PLL to a known good state before scaling for frequency. > >> The 'clk_alpha_pll_reconfigure()' can be updated to support more PLLs > >> in future. > > > > This sounds like a hack. You already describe the underlying problem (and > > indirectly its solution) in the first paragraph above, namely that the > > video clock controller has not enabled the power domain needed to > > configure the PLL. > > This is not a hack, but another alternative way to ensure the PLL is > configured to the right configuration before being used. I say it's a hack since it sounds like since you're relying on some other entity to have enabled resources that this clock controller depends on. > > I believe support for clock controllers that need to enable multiple > > power domains is on its way into 6.15: > > > > https://lore.kernel.org/lkml/20250117-b4-linux-next-24-11-18-clock-multiple-power-domains-v10-0-13f2bb656dad@linaro.org/ > > > > Perhaps that's what you need to fix this properly. > > Yes, this is just to add a dependency on clock controller to put the > rail vote, but this series does not fully solve the clock controller's > PLL requirement problems. Why not? What else is needed beyond enabling the video (?) power domain before configuring the PLL? Johan
During boot-up, there is a possibility that the PLL configuration might be missed even after invoking pll_configure() from the clock controller probe. This is often due to the PLL being connected to rail or rails that are in an OFF state and current clock controller also cannot vote on multiple rails. As a result, the PLL may be enabled with suboptimal settings, leading to functional issues. The PLL configuration, now part of clk_alpha_pll, can be reused to reconfigure the PLL to a known good state before scaling for frequency. The 'clk_alpha_pll_reconfigure()' can be updated to support more PLLs in future. The IRIS driver support added https://lore.kernel.org/all/20241212-qcom-video-iris-v9-0-e8c2c6bd4041@quicinc.com/ observes the pll latch warning during boot up due to the dependency of the PLL not in good state, thus add config support for SM8550 Video clock controller PLLs. Signed-off-by: Taniya Das <quic_tdas@quicinc.com> --- Taniya Das (3): clk: qcom: clk-alpha-pll: Integrate PLL configuration into PLL structure clk: qcom: clk-alpha-pll: Add support to reconfigure PLL clk: qcom: videocc-sm8550: Update the pll config for Video PLLs drivers/clk/qcom/clk-alpha-pll.c | 30 ++++++++++++++++++++++++++++++ drivers/clk/qcom/clk-alpha-pll.h | 2 ++ drivers/clk/qcom/videocc-sm8550.c | 2 ++ 3 files changed, 34 insertions(+) --- base-commit: 37136bf5c3a6f6b686d74f41837a6406bec6b7bc change-id: 20250113-support-pll-reconfigure-9a9cbb43a90b Best regards,