From patchwork Tue Jan 28 06:27:01 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 13952069 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AC47C1C5F27; Tue, 28 Jan 2025 06:27:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738045671; cv=none; b=Hab7iOj0vTsKThWEPhZNdXyWdBqTSD40Xuo4K2Vc+CJz0EGyOg5AI7kxJ+mi6hOd8gOl0mm0kH5qzvzepIa4YVB9DRO/gDPnhtL/iCTet0X2zqrqqWIR7xfTT9ZrnyHmfwUQP3QgXw6hhzJ8PgDP+U7Joc95ULMeZzM1iRtEGzw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738045671; c=relaxed/simple; bh=VRstfNY+f+k2s+kmSwD2IIdmczvjU0TYsseJ0PdD77E=; h=From:To:Subject:Date:Message-ID:MIME-Version:Content-Type; b=YGcSoPunocIZZPm61Q4bqYt9TxDUfW1iL5ys8TlvG0mDy0UEJ+Al2dkYRD5O7FsCeL0AgqSRqgfUWBpiCkGwFVG0qrPMgt40MVjXBV+QHFgLtK6OFlZkR1ZMFN7klkvrqiOzdWji8oIphnI6Kps+t5jxi9uXUJur5uzed/FM1JE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=b7u20+ez; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="b7u20+ez" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 50S0DgZY011267; Tue, 28 Jan 2025 06:27:26 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= content-transfer-encoding:content-type:date:from:message-id :mime-version:subject:to; s=qcppdkim1; bh=fvDrTGbxCU/3kI3NY9SZw9 ys3MPFMlKRkD+arB7AWvs=; b=b7u20+ezLNAdCEXft6f6L4OdBhqVtK2Dzid5Cm jfpgylmek6SHR5yBu6GAe5pKEMqrnWqShX0spnb4ImuWhg2yaOyDPIRzeRzxINZZ btmnuK26gdvxz4qXN39ydX0O+0Wr3BvLi0jRyH9sZUE1GiF2oAK5GlrVPDBoITC2 QnP1NXvuSaNdOnyq63eaUfl3pMtIDTj4MNrPUWBX9xDamRpTZeu0ky1680pN/ris 2YNpphNOfTRkxG148xYf16dwoBcGcHLUr3I9JoajHhsUstl6dj0pwGD/7oW6oOmR D7LblYP3RBTUffmCVB4mYl3EsL90iLF64RlHrhbNOcA0mspQ== Received: from nasanppmta04.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 44emgtrj10-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 28 Jan 2025 06:27:26 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 50S6RPUe018459 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 28 Jan 2025 06:27:25 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 27 Jan 2025 22:27:19 -0800 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , , , , , Subject: [PATCH v9 0/7] Add PCIe support for Qualcomm IPQ5332 Date: Tue, 28 Jan 2025 11:57:01 +0530 Message-ID: <20250128062708.573662-1-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: bYLQKs_UyIRXP1Wf_QAXDd2v7MXGq3Jb X-Proofpoint-GUID: bYLQKs_UyIRXP1Wf_QAXDd2v7MXGq3Jb X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-28_02,2025-01-27_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 suspectscore=0 adultscore=0 malwarescore=0 mlxlogscore=999 mlxscore=0 phishscore=0 impostorscore=0 priorityscore=1501 lowpriorityscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501280048 Patch series adds support for enabling the PCIe controller and UNIPHY found on Qualcomm IPQ5332 platform. PCIe0 is Gen3 X1 and PCIe1 is Gen3 X2 are added. This series combines [1] and [2]. [1] introduces IPQ5018 PCIe support and [2] depends on [1] to introduce IPQ5332 PCIe support. Since the community was interested in [2] (please see [3]), tried to revive IPQ5332's PCIe support with v2 of this patch series. v2 of this series pulled in the phy driver from [1] tried to address comments/feedback given in both [1] and [2]. 1. Enable IPQ5018 PCI support (Nitheesh Sekar) - https://lore.kernel.org/all/20231003120846.28626-1-quic_nsekar@quicinc.com/ 2. Add PCIe support for Qualcomm IPQ5332 (Praveenkumar I) - https://lore.kernel.org/linux-arm-msm/20231214062847.2215542-1-quic_ipkumar@quicinc.com/ 3. Community interest - https://lore.kernel.org/linux-arm-msm/20240310132915.GE3390@thinkpad/ v9: Dont have fallback for num-lanes in driver and return error Remove superfluous ipq5332 constraint as the fallback is present v8: Add reviewed by Remove duplication in bindings due to ipq5424 code getting merged v7: phy bindings: * Include data type definition to 'num-lanes' controller bindings: * Split the ipq9574 and ipq5332 changes into separate patches dtsi: * Add root port definitions v6: phy bindings: * Fix num-lanes definition phy driver: * Fix num-lanes handling in probe to use generally followed pattern controller bindings: * Give more info in commit log dtsi: * Add assigned-clocks & assigned-clock-rates to controller nodes * Add num-lanes to pcie0_phy v5: phy bindings: * Drop '3x1' & '3x2' from compatible string * Use 'num-lanes' to differentiate instead of '3x1' or '3x2' in compatible string * Describe clocks and resets instead of just maxItems phy driver: * Get num-lanes from DTS * Drop compatible specific init data as there is only one compatible string controller bindings: * Re-arrange 5332 and 9574 compatibles to handle fallback usage in dts dtsi: * Add 'num-lanes' to "pcie1_phy: phy@4b1000" * Make ipq5332 as main and ipq9574 as fallback compatible * Sort controller nodes per address misc: Add R-B tag from Konrad to dts and dtsi patches v4: * phy bindings - Create ipq5332 compatible instead of reusing ipq9574 for bindings * phy bindings - Remove reset-names as the resets are handled with bulk APIs * phy bindings - Fix order in the 'required' section * phy bindings - Remove clock-output-names * dtsi - Add missing reset for pcie1_phy * dtsi - Convert 'reg-names' to a vertical list * dts - Fix nodes sort order * dts - Use property-n followed by property-names v3: * Update the cover letter with the sources of the patches * Rename the dt-bindings yaml file similar to other phys * Drop ipq5332 specific pcie controllor bindings and reuse ipq9574 pcie controller bindings for ipq5332 * Please see patches for specific changes * Set GPL license for phy-qcom-uniphy-pcie-28lp.c v2: Address review comments from V1 Drop the 'required clocks' change that would break ABI (in dt-binding, dts, gcc-ipq5332.c) Include phy driver from the dependent series v1: https://lore.kernel.org/linux-arm-msm/20231214062847.2215542-1-quic_ipkumar@quicinc.com/ Nitheesh Sekar (2): dt-bindings: phy: qcom,uniphy-pcie: Document PCIe uniphy phy: qcom: Introduce PCIe UNIPHY 28LP driver Praveenkumar I (2): arm64: dts: qcom: ipq5332: Add PCIe related nodes arm64: dts: qcom: ipq5332-rdp441: Enable PCIe phys and controllers Varadarajan Narayanan (3): dt-bindings: PCI: qcom: Use sdx55 reg description for ipq9574 arm64: dts: qcom: ipq9574: Reorder reg and reg-names dt-bindings: PCI: qcom: Document the IPQ5332 PCIe controller .../devicetree/bindings/pci/qcom,pcie.yaml | 10 +- .../phy/qcom,ipq5332-uniphy-pcie-phy.yaml | 76 +++++ arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts | 76 +++++ arch/arm64/boot/dts/qcom/ipq5332.dtsi | 268 +++++++++++++++- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 52 ++-- drivers/phy/qualcomm/Kconfig | 12 + drivers/phy/qualcomm/Makefile | 1 + .../phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c | 287 ++++++++++++++++++ 8 files changed, 759 insertions(+), 23 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml create mode 100644 drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c base-commit: 5ffa57f6eecefababb8cbe327222ef171943b183