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Tue, 25 Mar 2025 05:30:26 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFUaP/3gTLNur6saCYHGHl+3SX9tZjQxxQncUBNKoOTE3PO3CfIu3oe05QxFaw8RHX2kA0xGA== X-Received: by 2002:a05:6a00:b84:b0:736:5b85:a911 with SMTP id d2e1a72fcca58-7390598e30cmr32350900b3a.8.1742905825712; Tue, 25 Mar 2025 05:30:25 -0700 (PDT) Received: from hu-prashk-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7390618e4b6sm9987391b3a.180.2025.03.25.05.30.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Mar 2025 05:30:25 -0700 (PDT) From: Prashanth K To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: cros-qcom-dts-watchers@chromium.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prashanth K Subject: [PATCH v1 0/5] Add snps,dis_u3_susphy_quirk for some QC targets Date: Tue, 25 Mar 2025 18:00:14 +0530 Message-Id: <20250325123019.597976-1-prashanth.k@oss.qualcomm.com> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Authority-Analysis: v=2.4 cv=Ybu95xRf c=1 sm=1 tr=0 ts=67e2a1f2 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=Vs1iUdzkB0EA:10 a=VwQbUJbxAAAA:8 a=COk6AnOGAAAA:8 a=1HEuz3GWIXJSLhVaKDMA:9 a=1OuFwYUASf3TG4hYMiVC:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: Fu41vYAm64XF-nr-LsAQn5pbOpvQP0QF X-Proofpoint-ORIG-GUID: Fu41vYAm64XF-nr-LsAQn5pbOpvQP0QF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-25_05,2025-03-25_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 impostorscore=0 suspectscore=0 mlxlogscore=672 priorityscore=1501 spamscore=0 lowpriorityscore=0 mlxscore=0 malwarescore=0 bulkscore=0 clxscore=1011 adultscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503250088 During device mode initialization on certain QC targets, before the runstop bit is set, sometimes it's observed that the GEVNTADR{LO/HI} register write fails. As a result, GEVTADDR registers are still 0x0. Upon setting runstop bit, DWC3 controller attempts to write the new events to address 0x0, causing an SMMU fault and system crash. More info about the crash at [1]. This was initially observed on SM8450 and later reported on few other targets as well. As suggested by Qualcomm HW team, clearing the GUSB3PIPECTL.SUSPHY bit resolves the issue by preventing register write failures. Address this by setting the snps,dis_u3_susphy_quirk to keep the GUSB3PIPECTL.SUSPHY bit cleared. This change was tested on multiple targets (SM8350, SM8450 QCS615 etc.) for over an year and hasn't exhibited any side effects. [1]: https://lore.kernel.org/all/fa94cbc9-e637-ba9b-8ec8-67c6955eca98@quicinc.com/ Prashanth K (3): arm64: dts: qcom: sm8150: Add snps,dis_u3_susphy_quirk arm64: dts: qcom: sm8350: Add snps,dis_u3_susphy_quirk arm64: dts: qcom: sm8450: Add snps,dis_u3_susphy_quirk Pratham Pratap (2): arm64: dts: qcom: qcs615: Add snps,dis_u3_susphy_quirk arm64: dts: qcom: qdu1000: Add snps,dis_u3_susphy_quirk arch/arm64/boot/dts/qcom/qcs615.dtsi | 2 ++ arch/arm64/boot/dts/qcom/qdu1000.dtsi | 1 + arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 ++ arch/arm64/boot/dts/qcom/sm8350.dtsi | 2 ++ arch/arm64/boot/dts/qcom/sm8450.dtsi | 1 + 5 files changed, 8 insertions(+) Reviewed-by: Konrad Dybcio