From patchwork Mon Oct 28 18:12:35 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Josh Cartwright X-Patchwork-Id: 3103861 Return-Path: X-Original-To: patchwork-linux-arm-msm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 650189F2B7 for ; Mon, 28 Oct 2013 19:14:15 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9644820381 for ; Mon, 28 Oct 2013 19:14:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 20F1520395 for ; Mon, 28 Oct 2013 19:14:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756262Ab3J1TOL (ORCPT ); Mon, 28 Oct 2013 15:14:11 -0400 Received: from smtp.codeaurora.org ([198.145.11.231]:45210 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754833Ab3J1TOJ (ORCPT ); Mon, 28 Oct 2013 15:14:09 -0400 Received: from smtp.codeaurora.org (localhost [127.0.0.1]) by smtp.codeaurora.org (Postfix) with ESMTP id 55C7813F29E; Mon, 28 Oct 2013 19:14:09 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 486) id 42DFB13F2AD; Mon, 28 Oct 2013 19:14:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from joshc.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com [67.52.129.61]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: joshc@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id DBFC613F29E; Mon, 28 Oct 2013 19:14:08 +0000 (UTC) Received: by joshc.qualcomm.com (Postfix, from userid 1000) id A92F460CFF; Mon, 28 Oct 2013 14:12:55 -0500 (CDT) Message-Id: <043d714725f8b6df1873047164d2d0e78778138b.1382985169.git.joshc@codeaurora.org> In-Reply-To: References: From: Josh Cartwright Date: Mon, 28 Oct 2013 13:12:35 -0500 To: Greg Kroah-Hartman , Pawel Moll , Mark Rutland , Stephen Warren , Ian Campbell , Kumar Gala Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Sagar Dharia , Gilad Avidov , Michael Bohan Subject: [PATCH v3 06/10] spmi: document the PMIC arbiter SPMI bindings X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Josh Cartwright --- .../bindings/spmi/qcom,spmi-pmic-arb.txt | 42 ++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt diff --git a/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt b/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt new file mode 100644 index 0000000..68949aa --- /dev/null +++ b/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt @@ -0,0 +1,42 @@ +Qualcomm SPMI Controller (PMIC Arbiter) + +The SPMI PMIC Arbiter is found on the Snapdragon 800 Series. It is an SPMI +controller with wrapping arbitration logic to allow for multiple on-chip +devices to control a single SPMI master. + +The PMIC Arbiter can also act as an interrupt controller, providing interrupts +to slave devices. + +See spmi.txt for the generic SPMI controller binding requirements for child +nodes. + +Required properties: +- compatible : should be "qcom,spmi-pmic-arb". +- reg-names : should be "core", "intr", "cnfg" +- reg : offset and length of the PMIC Arbiter Core register map. +- reg : offset and length of the PMIC Arbiter Interrupt controller register map. +- reg : offset and length of the PMIC Arbiter Configuration register map. +- #address-cells : must be set to 1 +- #size-cells : must be set to 0 +- interrupt-controller : indicates the PMIC arbiter is an interrupt controller +- #interrupt-cells = <4>: interrupts are specified as a 4-tuple: + cell 1: slave ID for the requested interrupt (0-15) + cell 2: peripheral ID for requested interrupt (0-255) + cell 3: the requested peripheral interrupt (0-7) + cell 4: interrupt flags indicating level-sense information, as defined in + dt-bindings/interrupt-controller/irq.h + +Example: + + qcom,spmi@fc4c0000 { + compatible = "qcom,spmi-pmic-arb"; + reg-names = "core", "intr", "cnfg"; + reg = <0xfc4cf000 0x1000>, + <0Xfc4cb000 0x1000>, + <0Xfc4ca000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + interrupt-controller; + #interrupt-cells = <4>; + };