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Thu, 3 Aug 2023 00:08:14 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::5111:16e8:5afe:1da1]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::5111:16e8:5afe:1da1%6]) with mapi id 15.20.6631.045; Thu, 3 Aug 2023 00:08:14 +0000 From: Jason Gunthorpe To: Andy Gross , Alim Akhtar , Bjorn Andersson , AngeloGioacchino Del Regno , Baolin Wang , Christophe Leroy , Gerald Schaefer , Heiko Stuebner , iommu@lists.linux.dev, Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kevin Tian , Konrad Dybcio , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-s390@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Russell King , linuxppc-dev@lists.ozlabs.org, Matthias Brugger , Matthew Rosato , Michael Ellerman , Nicholas Piggin , Orson Zhai , Rob Clark , Robin Murphy , Samuel Holland , Thierry Reding , Krishna Reddy , Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: Lu Baolu , Dmitry Osipenko , Marek Szyprowski , Nicolin Chen , Niklas Schnelle , Steven Price , Thierry Reding Subject: [PATCH v6 11/25] iommu/tegra-smmu: Implement an IDENTITY domain Date: Wed, 2 Aug 2023 21:07:58 -0300 Message-ID: <11-v6-e8114faedade+425-iommu_all_defdom_jgg@nvidia.com> In-Reply-To: <0-v6-e8114faedade+425-iommu_all_defdom_jgg@nvidia.com> References: X-ClientProxiedBy: MN2PR16CA0039.namprd16.prod.outlook.com (2603:10b6:208:234::8) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|MN0PR12MB5809:EE_ X-MS-Office365-Filtering-Correlation-Id: c3ff1e60-18b6-4324-5749-08db93b5bacd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: VJp5qCnymMI+GeUB1bykehnTkbZPXkqMRQpFCQ8N0UEm5Xvza73KjA12xbr5Lce/HMgHCipzF3c5tZy99EN1g2RAYRLiGegK6UDwcHNHo/2lXzfUyVa7JkqKvC8XqpxUnj/Ey9JxHeWuDDXiAQN88V+f8u4ogJ6YCdhL3D+vtFzRejwJ6fXgBZ0tnIH0Nq2jUNTWxXBrP4kbnXCW11F0LCYcbuI0bFo+jM6Btf9ppnerGSlRlICXdaiOMRESroZBhlhdQtg6t0nhC2asl4mPRWCQa/IuUjOZHo3MiHS6XMS8fewCZtLQLfPp3kaSGczw+hGHBbdMKZcVDGX/86rmM8/3m69T8ovXnplstb1K9FG13mWUmrSU8GAle7M7lVWrb/FejO0bZKhBL5sizX6ZeSJfpCGV6T3KeAdeIRKtsymJnvKVm+jqMyfog0/tFPu6VbIM2ox2pmSGgki8ilC6Sfia7X13cb23uE/blsUTPOTE5JTosGwFYuOyudqYsd8CX9nqU2DKNfQLEaodcu1WQoyX3DR/3jLITCQJsn9Kff/ZCgmWs+KIz+ZaaMtTdj6/NsEsBaCSFkcNcb0udzeKnIAaj4wWFdhJdEaBPWY9UGH9Mffp6tn7eCwJYgJ12QSXi3Q09WTYv32O5Dt6InUT3lPWvlS8zW/b0V9wtKtAbfhMzPZBMzwxZis4PZUeWv235D1dNJ8WA1AXJ+rBSTLDySHSvCXrdd2qDuH6lnW/SFWryJvDlBmUW6rZc0dL2efBpUQWrQY0ROD8kJZwZgtOBhJLRd+AokqYeuFLx17R5LRZH3bDhwyuY4ooa0dNYMxP0GpAsIwSLEEXsBCWDisrTw3WRdGoi5Dy1rKsrnv7MnX55v5LYdwSpAvkEo39EBamwzRALN7Aip9sOAuvtyIjzWINAzPVrf7r81yM6qxI0AIsvgdIR6XqrYTalejb/2bNThid/TllpUisoPjNVNWLamikGejjYaVXpRN4cQXws8Q1aHqblsvVY447DFaAaJI2mtmtIbXphIFS/rvU0Oe5wBr6v+5+iQrXh/sFXKhn7x1b0Lfaro7Q5TyzzhbpGEeK6hNk6e01SWI/wy+YUvh2/MKDTzP0egGe/YwCe8xQqV6mePVb1ruX6WKF2iasxrcGCEeFwGNRl5JjysfYRNo03NMfD+I/s2jvq6Py2i1aDKt0nhH3B3EsmdN0p1ckurtM6dgPi9IIOyTY/tsoI6oTE6QyYLVob04MOxU4NgOHc9F29+J+vcDSdSM1YB87ZeCu6s87wF5rp+nom2cpvbWu8V6XtZXJUJ1Z8u/8B1uGYuC1WiXxntNRTeHtAdv721LnisCPiN0zkL4SA6nW5iI1ZBJKdzXpzR9ltSo4dN/ocdweUzfZjHuqrrKEoxTYfICUVKnmkK1FCsk4isAjz5Uevy2EIf8tKXcNVrDd+7jZT1skzx34gBf1Hee1xXPCfY4Q1RzJAfemG9wfRBD1oULlxJtMjrao1Id35t8Ztztc4bV/ETyUrKK9774Is5360tkJ/eW/uwBIVHCWpLsW6ATdraAeQsGDUyLnBnr67e5DhxaV+x7QYJHxJiJ+YR3PjK1B X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: c3ff1e60-18b6-4324-5749-08db93b5bacd X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Aug 2023 00:08:13.8849 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 8lmFMrGjQKXSSTGK30q+jKWxCyvAPb7LRQthtTxFfdZgyNa2zmhv3cTQkgQyawjK X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5809 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org What tegra-smmu does during tegra_smmu_set_platform_dma() is actually putting the iommu into identity mode. Move to the new core support for ARM_DMA_USE_IOMMU by defining ops->identity_domain. Signed-off-by: Jason Gunthorpe Reviewed-by: Lu Baolu --- drivers/iommu/tegra-smmu.c | 37 ++++++++++++++++++++++++++++++++----- 1 file changed, 32 insertions(+), 5 deletions(-) diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c index 1cbf063ccf147a..f63f1d4f0bd10f 100644 --- a/drivers/iommu/tegra-smmu.c +++ b/drivers/iommu/tegra-smmu.c @@ -511,23 +511,39 @@ static int tegra_smmu_attach_dev(struct iommu_domain *domain, return err; } -static void tegra_smmu_set_platform_dma(struct device *dev) +static int tegra_smmu_identity_attach(struct iommu_domain *identity_domain, + struct device *dev) { struct iommu_domain *domain = iommu_get_domain_for_dev(dev); struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); - struct tegra_smmu_as *as = to_smmu_as(domain); - struct tegra_smmu *smmu = as->smmu; + struct tegra_smmu_as *as; + struct tegra_smmu *smmu; unsigned int index; if (!fwspec) - return; + return -ENODEV; + if (domain == identity_domain || !domain) + return 0; + + as = to_smmu_as(domain); + smmu = as->smmu; for (index = 0; index < fwspec->num_ids; index++) { tegra_smmu_disable(smmu, fwspec->ids[index], as->id); tegra_smmu_as_unprepare(smmu, as); } + return 0; } +static struct iommu_domain_ops tegra_smmu_identity_ops = { + .attach_dev = tegra_smmu_identity_attach, +}; + +static struct iommu_domain tegra_smmu_identity_domain = { + .type = IOMMU_DOMAIN_IDENTITY, + .ops = &tegra_smmu_identity_ops, +}; + static void tegra_smmu_set_pde(struct tegra_smmu_as *as, unsigned long iova, u32 value) { @@ -962,11 +978,22 @@ static int tegra_smmu_of_xlate(struct device *dev, return iommu_fwspec_add_ids(dev, &id, 1); } +static int tegra_smmu_def_domain_type(struct device *dev) +{ + /* + * FIXME: For now we want to run all translation in IDENTITY mode, due + * to some device quirks. Better would be to just quirk the troubled + * devices. + */ + return IOMMU_DOMAIN_IDENTITY; +} + static const struct iommu_ops tegra_smmu_ops = { + .identity_domain = &tegra_smmu_identity_domain, + .def_domain_type = &tegra_smmu_def_domain_type, .domain_alloc = tegra_smmu_domain_alloc, .probe_device = tegra_smmu_probe_device, .device_group = tegra_smmu_device_group, - .set_platform_dma_ops = tegra_smmu_set_platform_dma, .of_xlate = tegra_smmu_of_xlate, .pgsize_bitmap = SZ_4K, .default_domain_ops = &(const struct iommu_domain_ops) {