From patchwork Fri Aug 2 02:15:25 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Vaswani X-Patchwork-Id: 2837486 Return-Path: X-Original-To: patchwork-linux-arm-msm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id DC5FB9F479 for ; Fri, 2 Aug 2013 02:16:55 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9A3D720367 for ; Fri, 2 Aug 2013 02:16:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8F20C20360 for ; Fri, 2 Aug 2013 02:16:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751448Ab3HBCQh (ORCPT ); Thu, 1 Aug 2013 22:16:37 -0400 Received: from smtp.codeaurora.org ([198.145.11.231]:33324 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754365Ab3HBCQb (ORCPT ); Thu, 1 Aug 2013 22:16:31 -0400 Received: from smtp.codeaurora.org (localhost [127.0.0.1]) by smtp.codeaurora.org (Postfix) with ESMTP id 1FBA613EF6B; Fri, 2 Aug 2013 02:16:31 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 486) id 1193A13EFFA; Fri, 2 Aug 2013 02:16:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-8.4 required=5.0 tests=BAYES_00,KHOP_BIG_TO_CC, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from codeaurora.org (i-global252.qualcomm.com [199.106.103.252]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: rvaswani@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 0AA2213EF6B; Fri, 2 Aug 2013 02:16:30 +0000 (UTC) From: Rohit Vaswani To: David Brown Cc: Rohit Vaswani , Rob Herring , Pawel Moll , Mark Rutland , Stephen Warren , Ian Campbell , Rob Landley , Russell King , Daniel Walker , Bryan Huntsman , Lorenzo Pieralisi , Nicolas Pitre , devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org Subject: [RESEND PATCH 4/4] ARM: msm: Add support for 8974 SMP Date: Thu, 1 Aug 2013 19:15:25 -0700 Message-Id: <1375409725-22004-5-git-send-email-rvaswani@codeaurora.org> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1375409725-22004-1-git-send-email-rvaswani@codeaurora.org> References: <1375409725-22004-1-git-send-email-rvaswani@codeaurora.org> X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add the cpus bindings and the Kraitv2 release sequence to make SMP work for 2 cores on MSM8974. Signed-off-by: Rohit Vaswani --- Documentation/devicetree/bindings/arm/cpus.txt | 1 + arch/arm/boot/dts/msm8974.dts | 23 ++++++++ arch/arm/mach-msm/board-dt-8974.c | 3 + arch/arm/mach-msm/platsmp.c | 79 ++++++++++++++++++++++++++ 4 files changed, 106 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index 1132eac..7c3c677 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -52,6 +52,7 @@ For the ARM architecture every CPU node must contain the following properties: This should be one of: "qcom,scss" "qcom,kpssv1" + "qcom,kpssv2" Example: diff --git a/arch/arm/boot/dts/msm8974.dts b/arch/arm/boot/dts/msm8974.dts index c31c097..ef35a9b 100644 --- a/arch/arm/boot/dts/msm8974.dts +++ b/arch/arm/boot/dts/msm8974.dts @@ -7,6 +7,22 @@ compatible = "qcom,msm8974"; interrupt-parent = <&intc>; + cpus { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,krait"; + device_type = "cpu"; + enable-method = "qcom,kpssv2"; + + cpu@0 { + reg = <0>; + }; + + cpu@1 { + reg = <1>; + }; + }; + intc: interrupt-controller@f9000000 { compatible = "qcom,msm-qgic2"; interrupt-controller; @@ -23,4 +39,11 @@ <1 1 0xf08>; clock-frequency = <19200000>; }; + + kpss@f9012000 { + compatible = "qcom,kpss"; + reg = <0xf9012000 0x1000>, + <0xf9088000 0x1000>, + <0xf9098000 0x1000>; + }; }; diff --git a/arch/arm/mach-msm/board-dt-8974.c b/arch/arm/mach-msm/board-dt-8974.c index d7f84f2..06119f9 100644 --- a/arch/arm/mach-msm/board-dt-8974.c +++ b/arch/arm/mach-msm/board-dt-8974.c @@ -13,11 +13,14 @@ #include #include +#include "common.h" + static const char * const msm8974_dt_match[] __initconst = { "qcom,msm8974", NULL }; DT_MACHINE_START(MSM8974_DT, "Qualcomm MSM (Flattened Device Tree)") + .smp = smp_ops(msm_smp_ops), .dt_compat = msm8974_dt_match, MACHINE_END diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c index 82eb079..0fdae69 100644 --- a/arch/arm/mach-msm/platsmp.c +++ b/arch/arm/mach-msm/platsmp.c @@ -124,6 +124,80 @@ static int msm8960_release_secondary(unsigned int cpu) return 0; } +static int msm8974_release_secondary(unsigned int cpu) +{ + void __iomem *reg; + void __iomem *l2_saw_base; + struct device_node *dn = NULL; + unsigned apc_pwr_gate_ctl = 0x14; + unsigned reg_val; + + if (cpu == 0 || cpu >= num_possible_cpus()) + return -EINVAL; + + dn = of_find_compatible_node(dn, NULL, "qcom,kpss"); + if (!dn) { + pr_err("%s : Missing kpss node from device tree\n", __func__); + return -ENXIO; + } + + reg = of_iomap(dn, cpu+1); + if (!reg) + return -ENOMEM; + + pr_debug("Starting secondary CPU %d\n", cpu); + + /* Turn on the BHS, turn off LDO Bypass and power down LDO */ + reg_val = 0x403f0001; + writel_relaxed(reg_val, reg + apc_pwr_gate_ctl); + + /* complete the above write before the delay */ + mb(); + /* wait for the bhs to settle */ + udelay(1); + + /* Turn on BHS segments */ + reg_val |= 0x3f << 1; + writel_relaxed(reg_val, reg + apc_pwr_gate_ctl); + + /* complete the above write before the delay */ + mb(); + /* wait for the bhs to settle */ + udelay(1); + + /* Finally turn on the bypass so that BHS supplies power */ + reg_val |= 0x3f << 8; + writel_relaxed(reg_val, reg + apc_pwr_gate_ctl); + + /* enable max phases */ + l2_saw_base = of_iomap(dn, 0); + if (!l2_saw_base) { + return -ENOMEM; + } + writel_relaxed(0x10003, l2_saw_base + 0x1c); + mb(); + udelay(50); + + iounmap(l2_saw_base); + + writel_relaxed(0x021, reg+0x04); + mb(); + udelay(2); + + writel_relaxed(0x020, reg+0x04); + mb(); + udelay(2); + + writel_relaxed(0x000, reg+0x04); + mb(); + + writel_relaxed(0x080, reg+0x04); + mb(); + + iounmap(reg); + return 0; +} + static DEFINE_PER_CPU(int, cold_boot_done); static void boot_cold_cpu(unsigned int cpu) @@ -151,6 +225,11 @@ static void boot_cold_cpu(unsigned int cpu) msm8960_release_secondary(cpu); per_cpu(cold_boot_done, cpu) = true; } + } else if (!strcmp(enable_method, "qcom,kpssv2")) { + if (per_cpu(cold_boot_done, cpu) == false) { + msm8974_release_secondary(cpu); + per_cpu(cold_boot_done, cpu) = true; + } } else { pr_err("%s: Invalid enable-method property: %s\n", __func__, enable_method);