From patchwork Thu Aug 29 13:27:52 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ivan T. Ivanov" X-Patchwork-Id: 2851364 Return-Path: X-Original-To: patchwork-linux-arm-msm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 2135D9F271 for ; Thu, 29 Aug 2013 13:29:20 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A5BC520315 for ; Thu, 29 Aug 2013 13:29:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D4BDB201D6 for ; Thu, 29 Aug 2013 13:29:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753229Ab3H2N3P (ORCPT ); Thu, 29 Aug 2013 09:29:15 -0400 Received: from ns.mm-sol.com ([212.124.72.66]:40265 "EHLO extserv.mm-sol.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753106Ab3H2N3O (ORCPT ); Thu, 29 Aug 2013 09:29:14 -0400 Received: from iivanov-dev.int.mm-sol.com (unknown [172.18.0.3]) by extserv.mm-sol.com (Postfix) with ESMTPSA id 95264C68F; Thu, 29 Aug 2013 16:29:12 +0300 (EEST) From: "Ivan T. Ivanov" To: wsa@the-dreams.de Cc: rob.herring@calxeda.com, pawel.moll@arm.com, mark.rutland@arm.com, swarren@wwwdotorg.org, ian.campbell@citrix.com, rob@landley.net, grant.likely@linaro.org, gavidov@codeaurora.org, sdharia@codeaurora.org, alokc@codeaurora.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel, linux-arm-msm@vger.kernel.org, "Ivan T. Ivanov" Subject: [PATCH 1/2] i2c: qup: Add device tree bindings information Date: Thu, 29 Aug 2013 16:27:52 +0300 Message-Id: <1377782873-31931-1-git-send-email-iivanov@mm-sol.com> X-Mailer: git-send-email 1.7.9.5 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Spam-Status: No, score=-9.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: "Ivan T. Ivanov" The Qualcomm Universal Peripherial (QUP) wraps I2C mini-core and provide input and output FIFO's for it. I2C controller can operate as master with supported bus speeds of 100Kbps and 400Kbps. Signed-off-by: Ivan T. Ivanov --- Documentation/devicetree/bindings/i2c/i2c-qup.txt | 99 +++++++++++++++++++++ 1 file changed, 99 insertions(+) create mode 100644 Documentation/devicetree/bindings/i2c/i2c-qup.txt diff --git a/Documentation/devicetree/bindings/i2c/i2c-qup.txt b/Documentation/devicetree/bindings/i2c/i2c-qup.txt new file mode 100644 index 0000000..c682726 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/i2c-qup.txt @@ -0,0 +1,99 @@ +Qualcomm Universal Periferial (QUP) I2C controller + +Required properties: + - compatible : should be "qcom,i2c-qup" + - reg : Offset and length of the register region for the device + - interrupts : core interrupt + + - pinctrl-names: Should contain only one value - "default". + - pinctrl-0: Should specify pin control group used for this controller. + + - clocks : phandles to clock instances of the device tree nodes + - clock-names : + "core" : Allow access to FIFO buffers and registers + "iface" : Clock used by QUP interface + + - #address-cells : should be <1> Address cells for I2C device address + - #size-cells : should be <0> I2C addresses have no size component. + +Optional properties : + - Child nodes conforming to i2c bus binding + - clock-frequency : Desired I2C bus clock frequency in Hz. If + not set thedefault frequency is 100kHz + - qcom,src-freq : Frequency of the source clocking this bus in Hz. + Divider value is set based on soruce-frequency and + desired I2C bus frequency. If this value is not + provided, the source clock is assumed to be running + at 19.2 MHz. + +Aliases: An alias may optionally be used to bind the I2C controller +to bus number. Aliases are of the form i2c where is an integer +representing the bus number to use. + +Example: + + aliases { + i2c0 = &i2c_A; + i2c1 = &i2c_B; + i2c2 = &i2c_C; + }; + + i2c_A: i2c@f9967000 { + compatible = "qcom,i2c-qup"; + reg = <0Xf9967000 0x1000>; + interrupts = <0 105 0>; + + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_data>; + + clocks = <&core>, <&iface>; + clock-names = "core", "iface"; + + clock-frequency = <100000>; + qcom,src-freq = <50000000>; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + dummy@60 { + compatible = "dummy"; + reg = <0x60>; + }; + }; + + i2c_B: i2c@f9923000 { + compatible = "qcom,i2c-qup"; + reg = <0xf9923000 0x1000>; + interrupts = <0 95 0>; + + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_data>; + + clocks = <&core>, <&iface>; + clock-names = "core", "iface"; + + clock-frequency = <100000>; + qcom,src-freq = <19200000>; + + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c_C: i2c@f9924000 { + compatible = "qcom,i2c-qup"; + reg = <0xf9924000 0x1000>; + interrupts = <0 96 0>; + + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_data>; + + clocks = <&core>, <&iface>; + clock-names = "core", "iface"; + + clock-frequency = <100000>; + qcom,src-freq = <50000000>; + + #address-cells = <1>; + #size-cells = <0>; + };