From patchwork Wed Mar 12 17:17:24 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Josh Cartwright X-Patchwork-Id: 3819761 Return-Path: X-Original-To: patchwork-linux-arm-msm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 4032A9F1CD for ; Wed, 12 Mar 2014 17:20:59 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6BF59202DD for ; Wed, 12 Mar 2014 17:20:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7AE15202C8 for ; Wed, 12 Mar 2014 17:20:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754442AbaCLRU1 (ORCPT ); Wed, 12 Mar 2014 13:20:27 -0400 Received: from smtp.codeaurora.org ([198.145.11.231]:44349 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754160AbaCLRUY (ORCPT ); Wed, 12 Mar 2014 13:20:24 -0400 Received: from smtp.codeaurora.org (localhost [127.0.0.1]) by smtp.codeaurora.org (Postfix) with ESMTP id 1971A13F257; Wed, 12 Mar 2014 17:20:24 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 486) id 078D513F32A; Wed, 12 Mar 2014 17:20:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from joshc.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com [67.52.129.61]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: joshc@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 9D3B313F271; Wed, 12 Mar 2014 17:20:23 +0000 (UTC) Received: by joshc.qualcomm.com (Postfix, from userid 1000) id 2D35D6354B; Wed, 12 Mar 2014 12:17:25 -0500 (CDT) From: Josh Cartwright To: Andrew Morton , Alessandro Zummo , linux-kernel@vger.kernel.org, Lee Jones Cc: linux-arm-msm@vger.kernel.org, rtc-linux@googlegroups.com, Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Rob Landley , devicetree@vger.kernel.org, linux-doc@vger.kernel.org, Samuel Ortiz Subject: [PATCH v3 6/6] mfd: devicetree: bindings: add pm8xxx RTC description Date: Wed, 12 Mar 2014 12:17:24 -0500 Message-Id: <1394644645-12818-1-git-send-email-joshc@codeaurora.org> X-Mailer: git-send-email 1.9.0 In-Reply-To: <20140310151807.7274d58d3c50b884585244b6@linux-foundation.org> References: <20140310151807.7274d58d3c50b884585244b6@linux-foundation.org> X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The PM8xxx family of PMICs contain an RTC. This RTC is described as a subnode of the PM8xxx. Document these bindings, and replace the pwrkey node in the example with the RTC, which is now described in this document. While we're here, add a short description to the device tree bindings describing what the the PM8xxx devices are and how they are expected to be used. Signed-off-by: Josh Cartwright --- Andrew- Here's a new 6/6. Like mentioned earlier, this is based on the current MFD document that's in Lee's tree pending for 3.15. It may be best to get yours and Rob's Ack and have Lee take it through his tree. Thanks, Josh .../devicetree/bindings/mfd/qcom,pm8xxx.txt | 45 +++++++++++++++++++--- 1 file changed, 39 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/mfd/qcom,pm8xxx.txt b/Documentation/devicetree/bindings/mfd/qcom,pm8xxx.txt index e3fe625..03518dc 100644 --- a/Documentation/devicetree/bindings/mfd/qcom,pm8xxx.txt +++ b/Documentation/devicetree/bindings/mfd/qcom,pm8xxx.txt @@ -1,6 +1,9 @@ Qualcomm PM8xxx PMIC multi-function devices -PROPERTIES +The PM8xxx family of Power Management ICs are used to provide regulated +voltages and other various functionality to Qualcomm SoCs. + += PROPERTIES - compatible: Usage: required @@ -45,7 +48,37 @@ PROPERTIES Value type: Definition: identifies this node as an interrupt controller -EXAMPLE += SUBCOMPONENTS + +The PMIC contains multiple independent functions, each described in a subnode. +The below bindings specify the set of valid subnodes. + +== Real-Time Clock + +- compatible: + Usage: required + Value type: + Definition: must be one of: + "qcom,pm8058-rtc" + "qcom,pm8921-rtc" + +- reg: + Usage: required + Value type: + Definition: single entry specifying the base address of the RTC registers + +- interrupts: + Usage: required + Value type: + Definition: single entry specifying the RTC's alarm interrupt + +- allow-set-time: + Usage: optional + Value type: + Definition: indicates that the setting of RTC time is allowed by + the host CPU + += EXAMPLE pmicintc: pmic@0 { compatible = "qcom,pm8921"; @@ -55,9 +88,9 @@ EXAMPLE #address-cells = <1>; #size-cells = <0>; - pwrkey { - compatible = "qcom,pm8921-pwrkey"; - interrupt-parent = <&pmicintc>; - interrupts = <50 1>, <51 1>; + rtc@11d { + compatible = "qcom,pm8921-rtc"; + reg = <0x11d>; + interrupts = <0x27 0>; }; };