From patchwork Fri Apr 4 22:18:11 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tim Bird X-Patchwork-Id: 3941261 Return-Path: X-Original-To: patchwork-linux-arm-msm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 2948E9F1EE for ; Fri, 4 Apr 2014 22:19:01 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5D3402034E for ; Fri, 4 Apr 2014 22:19:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 80C272034C for ; Fri, 4 Apr 2014 22:18:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752064AbaDDWSc (ORCPT ); Fri, 4 Apr 2014 18:18:32 -0400 Received: from mail-pa0-f47.google.com ([209.85.220.47]:61118 "EHLO mail-pa0-f47.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751901AbaDDWS2 (ORCPT ); Fri, 4 Apr 2014 18:18:28 -0400 Received: by mail-pa0-f47.google.com with SMTP id lj1so4025616pab.6 for ; Fri, 04 Apr 2014 15:18:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=vMSlh+nZJWqS5N+XTNkztG777vkM/St/P2AecFBFSqk=; b=qvm5M5VYQoxTBPrHUPzMI2O7sdExtq4ydN/Bf0Kc+zZ4nxZPyC1+O3TULRHDVUpI8D rL1Ja4C2/UzaOdksh7MHTAg5a1gZVBZrVLOIvWJtRe/j0yr1zpq9nbcb1pLQ9MQwmaD0 GZ7yTKYtvnMLq9h1tcKFT6MKvOfzpmPUeUUvdq/geaoeYqQmqq5TV8bfVAjzBKCwED35 1QVuBDFGTp76wHrNEewY/DQ5iCVdTjnZFE2AGdfIbJfToLmc4OtV+Os/dC2gefiyMvPr RBtwQrUoX60MaRxkNcfqhWO+5enVzg+TaVvbGosczTYY97C9P8qJ6PutAb+YiLprP9rU w/0Q== X-Received: by 10.68.197.66 with SMTP id is2mr17577398pbc.96.1396649908284; Fri, 04 Apr 2014 15:18:28 -0700 (PDT) Received: from ussvlx8980.am.sony.com ([64.211.224.253]) by mx.google.com with ESMTPSA id e6sm20077400pbg.4.2014.04.04.15.18.27 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 04 Apr 2014 15:18:27 -0700 (PDT) From: Tim Bird To: iivanov@mm-sol.com Cc: linux-arm-msm@vger.kernel.org, galak@codeaurora.org, balbi@ti.com, davidb@codeaurora.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, Tim Bird Subject: [PATCH] usb: phy: msm: Select secondary PHY via TCSR Date: Fri, 4 Apr 2014 15:18:11 -0700 Message-Id: <1396649891-2880-1-git-send-email-tim.bird@sonymobile.com> X-Mailer: git-send-email 1.8.2.2 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Select the secondary PHY using the TCSR register, if phy-num=1 in the DTS (or phy_number is set in the platform data). The SOC has 2 PHYs which can be used with the OTG port, and this code allows configuring the correct one. Note: This resolves the problem I was seeing where I couldn't get the USB driver working at all on a dragonboard, from cold boot. This patch depends on patch 5/14 from Ivan's msm USB patch set. It does not use DT for the register address, as there's no evidence that this address changes between SoC versions. Signed-off-by: Tim Bird --- drivers/usb/phy/phy-msm-usb.c | 14 ++++++++++++++ include/linux/usb/msm_hsusb_hw.h | 3 +++ 2 files changed, 17 insertions(+) diff --git a/drivers/usb/phy/phy-msm-usb.c b/drivers/usb/phy/phy-msm-usb.c index c4820e6..0272489 100644 --- a/drivers/usb/phy/phy-msm-usb.c +++ b/drivers/usb/phy/phy-msm-usb.c @@ -1518,6 +1518,7 @@ static int __init msm_otg_probe(struct platform_device *pdev) struct resource *res; struct msm_otg *motg; struct usb_phy *phy; + void __iomem *phy_select; motg = devm_kzalloc(&pdev->dev, sizeof(struct msm_otg), GFP_KERNEL); if (!motg) { @@ -1580,6 +1581,19 @@ static int __init msm_otg_probe(struct platform_device *pdev) if (IS_ERR(motg->regs)) return PTR_ERR(motg->regs); + /* + * NOTE: The PHYs can be multiplexed between the chipidea controller + * and the dwc3 controller, using a single bit. It is important that + * the dwc3 driver does not set this bit in an incompatible way. + */ + if (motg->phy_number) { + phy_select = devm_ioremap_nocache(&pdev->dev, USB2_PHY_SEL, 4); + if (IS_ERR(phy_select)) + return PTR_ERR(phy_select); + /* Enable second PHY with the OTG port */ + writel_relaxed(0x1, phy_select); + } + dev_info(&pdev->dev, "OTG regs = %p\n", motg->regs); motg->irq = platform_get_irq(pdev, 0); diff --git a/include/linux/usb/msm_hsusb_hw.h b/include/linux/usb/msm_hsusb_hw.h index 575c743..10bf692 100644 --- a/include/linux/usb/msm_hsusb_hw.h +++ b/include/linux/usb/msm_hsusb_hw.h @@ -16,6 +16,9 @@ #ifndef __LINUX_USB_GADGET_MSM72K_UDC_H__ #define __LINUX_USB_GADGET_MSM72K_UDC_H__ +/* USB phy selector - in TCSR address range */ +#define USB2_PHY_SEL 0xfd4ab000 + #define USB_AHBBURST (MSM_USB_BASE + 0x0090) #define USB_AHBMODE (MSM_USB_BASE + 0x0098) #define USB_CAPLENGTH (MSM_USB_BASE + 0x0100) /* 8 bit */