From patchwork Tue Apr 8 15:51:16 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kumar Gala X-Patchwork-Id: 3949721 Return-Path: X-Original-To: patchwork-linux-arm-msm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 85F63BFF02 for ; Tue, 8 Apr 2014 15:51:39 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8D7FA203B8 for ; Tue, 8 Apr 2014 15:51:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 82106203AE for ; Tue, 8 Apr 2014 15:51:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756289AbaDHPvW (ORCPT ); Tue, 8 Apr 2014 11:51:22 -0400 Received: from smtp.codeaurora.org ([198.145.11.231]:35196 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756232AbaDHPvV (ORCPT ); Tue, 8 Apr 2014 11:51:21 -0400 Received: from smtp.codeaurora.org (localhost [127.0.0.1]) by smtp.codeaurora.org (Postfix) with ESMTP id 9F5AA13EDF1; Tue, 8 Apr 2014 15:51:20 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 486) id 8E49913EFD2; Tue, 8 Apr 2014 15:51:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-7.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from galak-ubuntu.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com [67.52.129.61]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: galak@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 0F78E13EF45; Tue, 8 Apr 2014 15:51:18 +0000 (UTC) From: Kumar Gala To: Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Russell King , David Brown Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org Subject: [PATCH v2] ARM: qcom: Add initial IPQ8064 SoC and AP148 device trees Date: Tue, 8 Apr 2014 10:51:16 -0500 Message-Id: <1396972276-11549-1-git-send-email-galak@codeaurora.org> X-Mailer: git-send-email 1.8.2.1 X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add basic IPQ8064 SoC include device tree and support for basic booting on the AP148 Reference board. Also, keep dtb build list and qcom_dt_match in sorted order. Signed-off-by: Kumar Gala --- v2: * created a v1.0 ipq8064.dtsi to handle differences in Si rev in future * changed /include/ to #include * fixed timer freq to be 25Mhz instead of 27Mhz (copied from msm8960) * added PMU node * dropped interrupts from cpus node, not currently part of binding arch/arm/boot/dts/Makefile | 8 +- arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 12 +++ arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi | 1 + arch/arm/boot/dts/qcom-ipq8064.dtsi | 125 +++++++++++++++++++++++++++++++ arch/arm/mach-qcom/board.c | 4 +- 5 files changed, 146 insertions(+), 4 deletions(-) create mode 100644 arch/arm/boot/dts/qcom-ipq8064-ap148.dts create mode 100644 arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi create mode 100644 arch/arm/boot/dts/qcom-ipq8064.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 4a89023..0591ed0 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -231,9 +231,11 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \ dra7-evm.dtb dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb -dtb-$(CONFIG_ARCH_QCOM) += qcom-msm8660-surf.dtb \ - qcom-msm8960-cdp.dtb \ - qcom-apq8074-dragonboard.dtb +dtb-$(CONFIG_ARCH_QCOM) += \ + qcom-apq8074-dragonboard.dtb \ + qcom-ipq8064-ap148.dtb \ + qcom-msm8660-surf.dtb \ + qcom-msm8960-cdp.dtb dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \ ste-hrefprev60-stuib.dtb \ ste-hrefprev60-tvk.dtb \ diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts new file mode 100644 index 0000000..5e6f456 --- /dev/null +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts @@ -0,0 +1,12 @@ +#include "qcom-ipq8064-v1.0.dtsi" + +/ { + model = "Qualcomm IPQ8064/DB149"; + compatible = "qcom,ipq8064-db149", "qcom,ipq8064"; + + soc { + serial@16340000 { + status = "ok"; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi new file mode 100644 index 0000000..7093b07 --- /dev/null +++ b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi @@ -0,0 +1 @@ +#include "qcom-ipq8064.dtsi" diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi new file mode 100644 index 0000000..8ca3b51 --- /dev/null +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -0,0 +1,125 @@ +/dts-v1/; + +#include "skeleton.dtsi" +#include + +/ { + model = "Qualcomm IPQ8064"; + compatible = "qcom,ipq8064"; + interrupt-parent = <&intc>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,krait"; + enable-method = "qcom,kpss-acc-v1"; + + cpu@0 { + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + qcom,acc = <&acc0>; + qcom,saw = <&saw0>; + }; + + cpu@1 { + device_type = "cpu"; + reg = <1>; + next-level-cache = <&L2>; + qcom,acc = <&acc1>; + qcom,saw = <&saw1>; + }; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; + interrupts = <0 2 0x4>; + }; + }; + + cpu-pmu { + compatible = "qcom,krait-pmu"; + interrupts = <1 10 0x304>; + }; + + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "simple-bus"; + + intc: interrupt-controller@2000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = < 0x02000000 0x1000 >, + < 0x02002000 0x1000 >; + }; + + timer@200a000 { + compatible = "qcom,kpss-timer", "qcom,msm-timer"; + interrupts = <1 1 0x301>, + <1 2 0x301>, + <1 3 0x301>; + reg = <0x0200a000 0x100>; + clock-frequency = <25000000>, + <32768>; + cpu-offset = <0x80000>; + }; + + acc0: clock-controller@2088000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x02088000 0x1000>, <0x02008000 0x1000>; + }; + + acc1: clock-controller@2098000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x02098000 0x1000>, <0x02008000 0x1000>; + }; + + saw0: regulator@2089000 { + compatible = "qcom,saw2"; + reg = <0x02089000 0x1000>, <0x02009000 0x1000>; + regulator; + }; + + saw1: regulator@2099000 { + compatible = "qcom,saw2"; + reg = <0x02099000 0x1000>, <0x02009000 0x1000>; + regulator; + }; + + serial@12490000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x12490000 0x1000>, + <0x12480000 0x1000>; + interrupts = <0 195 0x0>; + clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + serial@16340000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x16340000 0x1000>, + <0x16300000 0x1000>; + interrupts = <0 152 0x0>; + clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + qcom,ssbi@500000 { + compatible = "qcom,ssbi"; + reg = <0x00500000 0x1000>; + qcom,controller-type = "pmic-arbiter"; + }; + + gcc: clock-controller@900000 { + compatible = "qcom,gcc-ipq8064"; + reg = <0x00900000 0x4000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + }; +}; diff --git a/arch/arm/mach-qcom/board.c b/arch/arm/mach-qcom/board.c index bae617e..cb3c07c 100644 --- a/arch/arm/mach-qcom/board.c +++ b/arch/arm/mach-qcom/board.c @@ -15,9 +15,11 @@ #include static const char * const qcom_dt_match[] __initconst = { + "qcom,apq8074-dragonboard", + "qcom,ipq8062", + "qcom,ipq8064", "qcom,msm8660-surf", "qcom,msm8960-cdp", - "qcom,apq8074-dragonboard", NULL };