From patchwork Mon Jul 7 15:11:31 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ivan T. Ivanov" X-Patchwork-Id: 4495671 Return-Path: X-Original-To: patchwork-linux-arm-msm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id CAB7E9F3B4 for ; Mon, 7 Jul 2014 15:13:14 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E5C212018A for ; Mon, 7 Jul 2014 15:13:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id EF02E202E6 for ; Mon, 7 Jul 2014 15:13:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753543AbaGGPNJ (ORCPT ); Mon, 7 Jul 2014 11:13:09 -0400 Received: from ns.mm-sol.com ([37.157.136.199]:35836 "EHLO extserv.mm-sol.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751005AbaGGPMV (ORCPT ); Mon, 7 Jul 2014 11:12:21 -0400 Received: from iivanov-dev.wifi.mm-sol.com (unknown [37.157.136.206]) by extserv.mm-sol.com (Postfix) with ESMTPSA id 44175C7C8; Mon, 7 Jul 2014 18:12:19 +0300 (EEST) From: "Ivan T. Ivanov" To: Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala Cc: "Ivan T. Ivanov" , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH 2/4] pinctrl: qcom: Add documentation for pinctrl-qpnp binding Date: Mon, 7 Jul 2014 18:11:31 +0300 Message-Id: <1404745893-6379-3-git-send-email-iivanov@mm-sol.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1404745893-6379-1-git-send-email-iivanov@mm-sol.com> References: <1404745893-6379-1-git-send-email-iivanov@mm-sol.com> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: "Ivan T. Ivanov" DT binding documentation for qcom,pm8941-pinctrl and qcom,pm8841-pinctrl drivers. Signed-off-by: Ivan T. Ivanov --- .../bindings/pinctrl/qcom,qpnp-pinctrl.txt | 78 ++++++++++++++++++++++ 1 file changed, 78 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,qpnp-pinctrl.txt diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,qpnp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,qpnp-pinctrl.txt new file mode 100644 index 0000000..0b24860 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,qpnp-pinctrl.txt @@ -0,0 +1,78 @@ +Qualcomm Technologies (QTI) QPNP pinctrl controller + +Qualcomm Technologies (QTI) PMIC chips integrate SPMI based MPP (multiple +purpose pin) and GPIO pin configuration hardware modules. These modules control +the pin settings, including types/functions/directions/pulls/drive-strength/ +input/output, etc. + +They are two types of pins inside PMIC chips. Multi-Purpose Pin (MPP) and +General Purpuse Pins (GPIO) + +MPP pins are supporting following functions: +Digital Input, Digital Output, Analog Input, Analog Output and Current Sink + +GPIO pins are supporting following functions: +Digital Input, Digital Output + +Required Properties: + - compatible: Should contain "qcom,pm8941-pinctrl" or "qcom,pm8841-pinctrl". + - reg: MPP's configuration registers map offset + GPIO's configuration registers map offset - optional + - gpio-controller: Marks the device node as a GPIO controller. + - #gpio-cells : Should be two. + The first cell is the gpio pin number and the + second cell is used for optional parameters. + +Please refer to ../gpio/gpio.txt for a general description of GPIO bindings. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +Qualcomm's pin configuration nodes act as a container for an abitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those pin(s)/group(s), and various pin configuration +parameters, such as pull-up, drive strength, etc. + +The name of each subnode is not important; all subnodes should be enumerated +and processed purely based on their content. + +Each subnode only affects those parameters that are explicitly listed. In +other words, a subnode that lists a mux function but no pin configuration +parameters implies no information about any pin configuration parameters. +Similarly, a pin subnode that describes a pullup parameter implies no +information about e.g. the mux function. + +Valid functions for MPPs are gpio, mpp-ain, mpp-aout, mpp-cs. +Valid function for GPIOs is gpio. + +Valid names for PM8841 pins are mpp1-mpp4. +Valid names for PM8941 pins are mpp1-mpp8 and gpio1-gpio36. + +The following generic properties as defined in pinctrl-bindings.txt are valid +to specify in a GPIO pin configuration subnode: + + pins, function, bias-disable, bias-pull-down, bias-pull,up, drive-strength. + bias-high-impedance, drive-push-pull, drive-open-drain, drive-open-source, + input-enable, input-disable, power-source, output-low, output-high + +The following generic properties as defined in pinctrl-bindings.txt are valid +to specify in a MPP pin configuration subnode: + + pins, function, bias-disable, bias-pull,up, drive-strength. + bias-high-impedance, input-enable, input-disable, power-source, output-low, + output-high, + +The following non-standard properties are valid to specify in a MPP pin +configuration subnode: + qcom,ain-ctrl, qcom,aout-ctrl + +Example: + + pm8941_pinctrl: pins@a000 { + compatible = "qcom,pm8941-pinctrl"; + reg = <0xa000>, <0xc000>; + gpio-controller; + #gpio-cells = <2>; + };