From patchwork Tue Aug 12 12:05:02 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 4712491 Return-Path: X-Original-To: patchwork-linux-arm-msm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id D51C9C0338 for ; Tue, 12 Aug 2014 12:05:43 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id AFD612014A for ; Tue, 12 Aug 2014 12:05:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7E16D200E9 for ; Tue, 12 Aug 2014 12:05:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752894AbaHLMFQ (ORCPT ); Tue, 12 Aug 2014 08:05:16 -0400 Received: from mail-pd0-f175.google.com ([209.85.192.175]:38241 "EHLO mail-pd0-f175.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752879AbaHLMFO (ORCPT ); Tue, 12 Aug 2014 08:05:14 -0400 Received: by mail-pd0-f175.google.com with SMTP id r10so12559033pdi.34 for ; Tue, 12 Aug 2014 05:05:14 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5MNhnj3ISLscne+79QPJ7oFWTmcBHgjlNfdMvEcI1vk=; b=HX1RZQPQblPVGVx82sHDSLyAOk5g/Yr8Hi3ZbYEBkCwx0mVLXhEykDmX1iXbtY5wB1 6W+hJgPGQPf3eA4Ld9KDlHxrr4f5c1eIXtvuAiyjsUhGfLkkLghZQwQrIx9MDjaFpDk/ VSIGgYamO2ur8rF5U3cRiPoLzleOSgba/Sa4li7j53gPgJsx3u8NC8ghJ0jBAqX0OTN8 mnnJeJeLWyGT+RjbhuofmqQnEEofEwpzq0SdABfINYPAXCHgRsHj6VfUUoWOjrSx6iPx ZI8gnra4hoh3tQ9z1rRXGmA04WBmNr09Zw5N1rk2M68iBy4qC2zfbsYp9ZwQWa5sZ0pJ yH4A== X-Gm-Message-State: ALoCoQkHeZ1o6+/dteymNbwq+lyirmsUmUr3Lh1PuzsgSazA1czjeiTyuQ89cdsjf5Hr7SZ9Fpyw X-Received: by 10.70.0.48 with SMTP id 16mr3910052pdb.8.1407845114064; Tue, 12 Aug 2014 05:05:14 -0700 (PDT) Received: from localhost.localdomain ([117.198.92.185]) by mx.google.com with ESMTPSA id pd1sm13451078pdb.76.2014.08.12.05.05.08 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 12 Aug 2014 05:05:12 -0700 (PDT) From: Srinivas Kandagatla X-Google-Original-From: Srinivas Kandagatla To: linux-mmc@vger.kernel.org Cc: Linus Walleij , Chris Ball , Ulf Hansson , Russell King , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH RFC 4/5] mmc: mmci: Add sdio enable mask in variant data Date: Tue, 12 Aug 2014 13:05:02 +0100 Message-Id: <1407845102-8402-1-git-send-email-srinivas.kandadgatla@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1407844950-8072-1-git-send-email-srinivas.kandadgatla@linaro.org> References: <1407844950-8072-1-git-send-email-srinivas.kandadgatla@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_WEB, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Srinivas Kandagatla This patch adds sdio enable mask in variant data, SOCs like ST have special bits in datactrl register to enable sdio. Unconditionally setting this bit in this driver breaks other SOCs like Qualcomm which maps this bits to something else, so making this enable bit to come from variant data solves the issue. Originally the issue is detected while testing WLAN ath6kl on Qualcomm APQ8064. Signed-off-by: Srinivas Kandagatla Reviewed-by: Linus Walleij --- drivers/mmc/host/mmci.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index 747aba0..848e2bb 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c @@ -67,6 +67,7 @@ static unsigned int fmax = 515633; * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register * @blksz_datactrl4: true if Block size is at b4..b16 position in datactrl * register + * @datactrl_mask_sdio: SDIO enable mask in datactrl register * @pwrreg_powerup: power up value for MMCIPOWER register * @f_max: maximum clk frequency supported by the controller. * @signal_direction: input/out direction of bus signals can be indicated @@ -87,6 +88,7 @@ struct variant_data { unsigned int fifohalfsize; unsigned int data_cmd_enable; unsigned int datactrl_mask_ddrmode; + unsigned int datactrl_mask_sdio; bool sdio; bool st_clkdiv; bool blksz_datactrl16; @@ -133,6 +135,7 @@ static struct variant_data variant_u300 = { .clkreg_enable = MCI_ST_U300_HWFCEN, .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, .datalength_bits = 16, + .datactrl_mask_sdio = MCI_ST_DPSM_SDIOEN, .sdio = true, .pwrreg_powerup = MCI_PWR_ON, .f_max = 100000000, @@ -146,6 +149,7 @@ static struct variant_data variant_nomadik = { .fifohalfsize = 8 * 4, .clkreg = MCI_CLK_ENABLE, .datalength_bits = 24, + .datactrl_mask_sdio = MCI_ST_DPSM_SDIOEN, .sdio = true, .st_clkdiv = true, .pwrreg_powerup = MCI_PWR_ON, @@ -163,6 +167,7 @@ static struct variant_data variant_ux500 = { .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, .datalength_bits = 24, + .datactrl_mask_sdio = MCI_ST_DPSM_SDIOEN, .sdio = true, .st_clkdiv = true, .pwrreg_powerup = MCI_PWR_ON, @@ -182,6 +187,7 @@ static struct variant_data variant_ux500v2 = { .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, .datactrl_mask_ddrmode = MCI_ST_DPSM_DDRMODE, .datalength_bits = 24, + .datactrl_mask_sdio = MCI_ST_DPSM_SDIOEN, .sdio = true, .st_clkdiv = true, .blksz_datactrl16 = true, @@ -811,16 +817,10 @@ static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) if (data->flags & MMC_DATA_READ) datactrl |= MCI_DPSM_DIRECTION; - /* The ST Micro variants has a special bit to enable SDIO */ if (variant->sdio && host->mmc->card) if (mmc_card_sdio(host->mmc->card)) { - /* - * The ST Micro variants has a special bit - * to enable SDIO. - */ u32 clk; - - datactrl |= MCI_ST_DPSM_SDIOEN; + datactrl |= variant->datactrl_mask_sdio; /* * The ST Micro variant for SDIO small write transfers