From patchwork Fri Aug 22 04:54:55 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 4761311 Return-Path: X-Original-To: patchwork-linux-arm-msm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id C0166C0338 for ; Fri, 22 Aug 2014 04:56:06 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id F33B82017A for ; Fri, 22 Aug 2014 04:56:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 265E620179 for ; Fri, 22 Aug 2014 04:56:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755832AbaHVEzN (ORCPT ); Fri, 22 Aug 2014 00:55:13 -0400 Received: from mail-pd0-f180.google.com ([209.85.192.180]:33800 "EHLO mail-pd0-f180.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755856AbaHVEzM (ORCPT ); Fri, 22 Aug 2014 00:55:12 -0400 Received: by mail-pd0-f180.google.com with SMTP id v10so15220705pde.11 for ; Thu, 21 Aug 2014 21:55:11 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3EXghVLQAKu4e+eVW1HT1x1oNPl6AbQ/5jKvZYMchj0=; b=eO6wa523oxWJ+VaphHOIvVEBm9YvHGqsfrMBTKej0AMr4X+cDgoEzizXnAPnclq6D6 j2QV9Iqs+JyAhrc0yEGNWA0znbMyQrLEe1/+7CyN1os2AnXQB9/W7uWwg8Zkh/fsn7m3 UcV+To79K7w5h29tXWMo+HS0najhBPwGkTMxPDdG4aK/hOiWz3rTLmneSiq6jrJfC1KI qg7CsWoie1Jls1mLfDYAScuc3c3bs39pF3XA6/yiRptLF/GyngCl4eRoVZG4baKOSraH 3L44HuBQVSOsEZ+Ynfx7QX1FaP37H9eopvtqt39drBRLikE2ORG4znZBjkncvuu6xmu/ irkQ== X-Gm-Message-State: ALoCoQl1HP0CSbJnT2CM+YbHHIOJ4t5IJP7/gk9het4eAp2J9WzWjB5hHX8iaHSJTKUXfRhyTKhh X-Received: by 10.68.65.101 with SMTP id w5mr3341828pbs.5.1408683311607; Thu, 21 Aug 2014 21:55:11 -0700 (PDT) Received: from localhost.localdomain ([117.198.85.175]) by mx.google.com with ESMTPSA id gs2sm27222005pbc.20.2014.08.21.21.55.06 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 21 Aug 2014 21:55:10 -0700 (PDT) From: Srinivas Kandagatla To: linux-mmc@vger.kernel.org Cc: Linus Walleij , Chris Ball , Ulf Hansson , Russell King , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH v3 2/3] mmc: mmci: Add sdio enable mask in variant data Date: Fri, 22 Aug 2014 05:54:55 +0100 Message-Id: <1408683295-8030-1-git-send-email-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1408683219-7939-1-git-send-email-srinivas.kandagatla@linaro.org> References: <1408683219-7939-1-git-send-email-srinivas.kandagatla@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds sdio enable mask in variant data, SOCs like ST have special bits in datactrl register to enable sdio. Unconditionally setting this bit in this driver breaks other SOCs like Qualcomm which maps this bits to something else, so making this enable bit to come from variant data solves the issue. Originally the issue is detected while testing WLAN ath6kl on Qualcomm APQ8064. Reviewed-by: Linus Walleij Signed-off-by: Srinivas Kandagatla --- drivers/mmc/host/mmci.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index 533ad2b..a25759e 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c @@ -67,6 +67,7 @@ static unsigned int fmax = 515633; * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register * @blksz_datactrl4: true if Block size is at b4..b16 position in datactrl * register + * @datactrl_mask_sdio: SDIO enable mask in datactrl register * @pwrreg_powerup: power up value for MMCIPOWER register * @f_max: maximum clk frequency supported by the controller. * @signal_direction: input/out direction of bus signals can be indicated @@ -89,6 +90,7 @@ struct variant_data { unsigned int fifohalfsize; unsigned int data_cmd_enable; unsigned int datactrl_mask_ddrmode; + unsigned int datactrl_mask_sdio; bool sdio; bool st_clkdiv; bool blksz_datactrl16; @@ -138,6 +140,7 @@ static struct variant_data variant_u300 = { .clkreg_enable = MCI_ST_U300_HWFCEN, .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, .datalength_bits = 16, + .datactrl_mask_sdio = MCI_ST_DPSM_SDIOEN, .sdio = true, .pwrreg_powerup = MCI_PWR_ON, .f_max = 100000000, @@ -151,6 +154,7 @@ static struct variant_data variant_nomadik = { .fifohalfsize = 8 * 4, .clkreg = MCI_CLK_ENABLE, .datalength_bits = 24, + .datactrl_mask_sdio = MCI_ST_DPSM_SDIOEN, .sdio = true, .st_clkdiv = true, .pwrreg_powerup = MCI_PWR_ON, @@ -168,6 +172,7 @@ static struct variant_data variant_ux500 = { .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, .datalength_bits = 24, + .datactrl_mask_sdio = MCI_ST_DPSM_SDIOEN, .sdio = true, .st_clkdiv = true, .pwrreg_powerup = MCI_PWR_ON, @@ -187,6 +192,7 @@ static struct variant_data variant_ux500v2 = { .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, .datactrl_mask_ddrmode = MCI_ST_DPSM_DDRMODE, .datalength_bits = 24, + .datactrl_mask_sdio = MCI_ST_DPSM_SDIOEN, .sdio = true, .st_clkdiv = true, .blksz_datactrl16 = true, @@ -812,16 +818,10 @@ static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) if (data->flags & MMC_DATA_READ) datactrl |= MCI_DPSM_DIRECTION; - /* The ST Micro variants has a special bit to enable SDIO */ if (variant->sdio && host->mmc->card) if (mmc_card_sdio(host->mmc->card)) { - /* - * The ST Micro variants has a special bit - * to enable SDIO. - */ u32 clk; - - datactrl |= MCI_ST_DPSM_SDIOEN; + datactrl |= variant->datactrl_mask_sdio; /* * The ST Micro variant for SDIO small write transfers