From patchwork Tue Jan 27 22:10:42 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Gross X-Patchwork-Id: 5720971 Return-Path: X-Original-To: patchwork-linux-arm-msm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 22AC1BFFA8 for ; Tue, 27 Jan 2015 22:12:39 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5402D20254 for ; Tue, 27 Jan 2015 22:12:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7BCB720212 for ; Tue, 27 Jan 2015 22:12:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932118AbbA0WLr (ORCPT ); Tue, 27 Jan 2015 17:11:47 -0500 Received: from smtp.codeaurora.org ([198.145.11.231]:38519 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753842AbbA0WKv (ORCPT ); Tue, 27 Jan 2015 17:10:51 -0500 Received: from smtp.codeaurora.org (localhost [127.0.0.1]) by smtp.codeaurora.org (Postfix) with ESMTP id 225D4140F71; Tue, 27 Jan 2015 22:10:51 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 486) id 09E67140F73; Tue, 27 Jan 2015 22:10:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from localhost (rrcs-67-52-129-61.west.biz.rr.com [67.52.129.61]) (using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) (Authenticated sender: agross@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 52DAC140F72; Tue, 27 Jan 2015 22:10:50 +0000 (UTC) From: Andy Gross To: linux-arm-msm@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Bjorn Andersson , devicetree@vger.kernel.org, Kumar Gala , linux-soc@vger.kernel.org, Andy Gross Subject: [PATCH 4/6] ARM: DT: ipq8064: Add TCSR support Date: Tue, 27 Jan 2015 16:10:42 -0600 Message-Id: <1422396644-21714-5-git-send-email-agross@codeaurora.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1422396644-21714-1-git-send-email-agross@codeaurora.org> References: <1422396644-21714-1-git-send-email-agross@codeaurora.org> X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds TCSR support for use by the GSBI to automatically configure ADM CRCI values based on the GSBI port configuration. Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-ipq8064.dtsi | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 63b2146..e47358d 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -119,7 +119,7 @@ }; gsbi2: gsbi@12480000 { - compatible = "qcom,gsbi-v1.0.0"; + compatible = "qcom,gsbi-ipq8064"; reg = <0x12480000 0x100>; clocks = <&gcc GSBI2_H_CLK>; clock-names = "iface"; @@ -128,6 +128,9 @@ ranges; status = "disabled"; + qcom,gsbi-num = <2>; + syscon-tcsr = <&tcsr>; + serial@12490000 { compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x12490000 0x1000>, @@ -154,7 +157,7 @@ }; gsbi4: gsbi@16300000 { - compatible = "qcom,gsbi-v1.0.0"; + compatible = "qcom,gsbi-ipq8064"; reg = <0x16300000 0x100>; clocks = <&gcc GSBI4_H_CLK>; clock-names = "iface"; @@ -163,6 +166,9 @@ ranges; status = "disabled"; + qcom,gsbi-num = <4>; + syscon-tcsr = <&tcsr>; + serial@16340000 { compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x16340000 0x1000>, @@ -188,7 +194,7 @@ }; gsbi5: gsbi@1a200000 { - compatible = "qcom,gsbi-v1.0.0"; + compatible = "qcom,gsbi-ipq8064"; reg = <0x1a200000 0x100>; clocks = <&gcc GSBI5_H_CLK>; clock-names = "iface"; @@ -197,6 +203,9 @@ ranges; status = "disabled"; + qcom,gsbi-num = <5>; + syscon-tcsr = <&tcsr>; + serial@1a240000 { compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x1a240000 0x1000>, @@ -279,5 +288,10 @@ #clock-cells = <1>; #reset-cells = <1>; }; + + tcsr: syscon@1a400000 { + compatible = "qcom,tcsr-ipq8064", "syscon"; + reg = <0x1a400000 0x100>; + }; }; };