From patchwork Wed Jul 22 07:11:01 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 6840421 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: X-Original-To: patchwork-linux-arm-msm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id B4EDE9F380 for ; Wed, 22 Jul 2015 07:11:52 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0FAFA206F0 for ; Wed, 22 Jul 2015 07:11:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 29C6C20710 for ; Wed, 22 Jul 2015 07:11:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756130AbbGVHLt (ORCPT ); Wed, 22 Jul 2015 03:11:49 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:60350 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755889AbbGVHLs (ORCPT ); Wed, 22 Jul 2015 03:11:48 -0400 Received: from smtp.codeaurora.org (localhost [127.0.0.1]) by smtp.codeaurora.org (Postfix) with ESMTP id E100B140D20; Wed, 22 Jul 2015 07:11:47 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 486) id D2062140D29; Wed, 22 Jul 2015 07:11:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-8.1 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from blr-ubuntu-34.ap.qualcomm.com (unknown [202.46.23.61]) (using TLSv1.1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: rnayak@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 04E95140D20; Wed, 22 Jul 2015 07:11:43 +0000 (UTC) From: Rajendra Nayak To: sboyd@codeaurora.org, mturquette@baylibre.com Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, georgi.djakov@linaro.org, svarbanov@mm-sol.com, srinivas.kandagatla@linaro.org, sviau@codeaurora.org, Rajendra Nayak Subject: [PATCH v6 05/13] clk: qcom: gdsc: Enable an RCG before turing on the gdsc Date: Wed, 22 Jul 2015 12:41:01 +0530 Message-Id: <1437549069-29655-6-git-send-email-rnayak@codeaurora.org> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1437549069-29655-1-git-send-email-rnayak@codeaurora.org> References: <1437549069-29655-1-git-send-email-rnayak@codeaurora.org> X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some gdsc instances require a certain root clock (RCG) to be turned on *before* the power domain itself can be turned on. Handle this as part of the gdsc enable/disable callbacks. Signed-off-by: Rajendra Nayak --- drivers/clk/qcom/gdsc.c | 20 +++++++++++++++++++- drivers/clk/qcom/gdsc.h | 5 +++++ 2 files changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c index 9ddd2f8..fc0aa7c 100644 --- a/drivers/clk/qcom/gdsc.c +++ b/drivers/clk/qcom/gdsc.c @@ -84,6 +84,9 @@ static int gdsc_enable(struct generic_pm_domain *domain) struct gdsc *sc = domain_to_gdsc(domain); int ret; + if (sc->root_clk) + clk_prepare_enable(sc->root_clk); + ret = gdsc_toggle_logic(sc, true); if (ret) return ret; @@ -101,9 +104,15 @@ static int gdsc_enable(struct generic_pm_domain *domain) static int gdsc_disable(struct generic_pm_domain *domain) { + int ret; struct gdsc *sc = domain_to_gdsc(domain); - return gdsc_toggle_logic(sc, false); + ret = gdsc_toggle_logic(sc, false); + + if (sc->root_clk) + clk_disable_unprepare(sc->root_clk); + + return ret; } static int gdsc_attach(struct generic_pm_domain *domain, struct device *dev) @@ -125,6 +134,15 @@ static int gdsc_attach(struct generic_pm_domain *domain, struct device *dev) goto fail; } } + + if (sc->root_con_id) { + sc->root_clk = clk_get(dev, sc->root_con_id); + if (IS_ERR(sc->root_clk)) { + dev_err(dev, "failed to get root clock\n"); + return PTR_ERR(sc->root_clk); + } + } + return 0; fail: pm_clk_destroy(dev); diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h index e26a496..a3abbea 100644 --- a/drivers/clk/qcom/gdsc.h +++ b/drivers/clk/qcom/gdsc.h @@ -14,6 +14,7 @@ #ifndef __QCOM_GDSC_H__ #define __QCOM_GDSC_H__ +#include #include #include @@ -22,11 +23,15 @@ * @pd: generic power domain * @regmap: regmap for MMIO accesses * @gdscr: gsdc control register + * @root_con_id: root clock to be enabled + * @root_clk: clk handle for the root clk */ struct gdsc { struct generic_pm_domain pd; struct regmap *regmap; unsigned int gdscr; + char *root_con_id; + struct clk *root_clk; }; #ifdef CONFIG_QCOM_GDSC