From patchwork Tue Jul 28 09:33:56 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 6881331 Return-Path: X-Original-To: patchwork-linux-arm-msm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id EE039C05AC for ; Tue, 28 Jul 2015 09:35:50 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 23E5D205BE for ; Tue, 28 Jul 2015 09:35:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 128BE206A7 for ; Tue, 28 Jul 2015 09:35:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755331AbbG1Jfm (ORCPT ); Tue, 28 Jul 2015 05:35:42 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:57387 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754069AbbG1JfI (ORCPT ); Tue, 28 Jul 2015 05:35:08 -0400 Received: from smtp.codeaurora.org (localhost [127.0.0.1]) by smtp.codeaurora.org (Postfix) with ESMTP id B3D571412CD; Tue, 28 Jul 2015 09:35:07 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 486) id 9E07F1412DB; Tue, 28 Jul 2015 09:35:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from blr-ubuntu-34.ap.qualcomm.com (unknown [202.46.23.61]) (using TLSv1.1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: rnayak@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id E181B1412CD; Tue, 28 Jul 2015 09:35:03 +0000 (UTC) From: Rajendra Nayak To: sboyd@codeaurora.org, mturquette@baylibre.com Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, georgi.djakov@linaro.org, svarbanov@mm-sol.com, srinivas.kandagatla@linaro.org, sviau@codeaurora.org, Rajendra Nayak Subject: [PATCH v7 03/13] clk: qcom: gdsc: Use PM clocks to control gdsc clocks Date: Tue, 28 Jul 2015 15:03:56 +0530 Message-Id: <1438076046-4706-4-git-send-email-rnayak@codeaurora.org> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1438076046-4706-1-git-send-email-rnayak@codeaurora.org> References: <1438076046-4706-1-git-send-email-rnayak@codeaurora.org> X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The devices within a gdsc power domain, quite often have additional clocks to be turned on/off along with the power domain itself. Once the drivers for these devices are converted to use runtime PM, it would be possible to remove all clock handling from the drivers if the gdsc driver can handle it. Use PM clocks to add support for this. A list of con_ids[] specified per gdsc would be the clocks turned on/off on every device start/stop callbacks. Signed-off-by: Rajendra Nayak --- drivers/clk/qcom/gdsc.c | 42 ++++++++++++++++++++++++++++++++++++++++++ drivers/clk/qcom/gdsc.h | 2 ++ 2 files changed, 44 insertions(+) diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c index 3b11f4d..68b810a 100644 --- a/drivers/clk/qcom/gdsc.c +++ b/drivers/clk/qcom/gdsc.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -108,6 +109,44 @@ static int gdsc_disable(struct generic_pm_domain *domain) return gdsc_toggle_logic(sc, false); } +static int gdsc_attach(struct generic_pm_domain *domain, struct device *dev) +{ + int ret; + struct gdsc *sc = domain_to_gdsc(domain); + const char **con_id; + + if (!sc->con_ids[0]) + return 0; + + ret = pm_clk_create(dev); + if (ret) { + dev_dbg(dev, "pm_clk_create failed %d\n", ret); + return ret; + } + + for (con_id = sc->con_ids; *con_id; con_id++) { + ret = pm_clk_add(dev, *con_id); + if (ret) { + dev_dbg(dev, "pm_clk_add failed %d\n", ret); + goto fail; + } + } + return 0; +fail: + pm_clk_destroy(dev); + return ret; +}; + +static void gdsc_detach(struct generic_pm_domain *domain, struct device *dev) +{ + struct gdsc *sc = domain_to_gdsc(domain); + + if (!sc->con_ids[0]) + return; + + pm_clk_destroy(dev); +}; + static int gdsc_init(struct gdsc *sc) { u32 mask, val; @@ -131,6 +170,9 @@ static int gdsc_init(struct gdsc *sc) sc->pd.power_off = gdsc_disable; sc->pd.power_on = gdsc_enable; + sc->pd.attach_dev = gdsc_attach; + sc->pd.detach_dev = gdsc_detach; + sc->pd.flags = GENPD_FLAG_PM_CLK; pm_genpd_init(&sc->pd, NULL, !on); return 0; diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h index f578a0c..68bcda3 100644 --- a/drivers/clk/qcom/gdsc.h +++ b/drivers/clk/qcom/gdsc.h @@ -24,11 +24,13 @@ struct regmap; * @pd: generic power domain * @regmap: regmap for MMIO accesses * @gdscr: gsdc control register + * @con_ids: List of clocks to be controlled for the gdsc */ struct gdsc { struct generic_pm_domain pd; struct regmap *regmap; unsigned int gdscr; + const char *con_ids[]; }; #ifdef CONFIG_QCOM_GDSC