From patchwork Tue Jul 28 09:33:58 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 6881221 Return-Path: X-Original-To: patchwork-linux-arm-msm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id AFD06C05AC for ; Tue, 28 Jul 2015 09:35:27 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id BED452050E for ; Tue, 28 Jul 2015 09:35:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D64442056C for ; Tue, 28 Jul 2015 09:35:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755286AbbG1JfU (ORCPT ); Tue, 28 Jul 2015 05:35:20 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:57416 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755260AbbG1JfR (ORCPT ); Tue, 28 Jul 2015 05:35:17 -0400 Received: from smtp.codeaurora.org (localhost [127.0.0.1]) by smtp.codeaurora.org (Postfix) with ESMTP id 84F771412E0; Tue, 28 Jul 2015 09:35:16 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 486) id 684791412E6; Tue, 28 Jul 2015 09:35:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from blr-ubuntu-34.ap.qualcomm.com (unknown [202.46.23.61]) (using TLSv1.1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: rnayak@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 3E6F01412E0; Tue, 28 Jul 2015 09:35:11 +0000 (UTC) From: Rajendra Nayak To: sboyd@codeaurora.org, mturquette@baylibre.com Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, georgi.djakov@linaro.org, svarbanov@mm-sol.com, srinivas.kandagatla@linaro.org, sviau@codeaurora.org, Rajendra Nayak Subject: [PATCH v7 05/13] clk: qcom: gdsc: Enable an RCG before turing on the gdsc Date: Tue, 28 Jul 2015 15:03:58 +0530 Message-Id: <1438076046-4706-6-git-send-email-rnayak@codeaurora.org> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1438076046-4706-1-git-send-email-rnayak@codeaurora.org> References: <1438076046-4706-1-git-send-email-rnayak@codeaurora.org> X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some gdsc instances require a certain root clock (RCG) to be turned on *before* the power domain itself can be turned on. Handle this as part of the gdsc enable/disable callbacks. Signed-off-by: Rajendra Nayak --- drivers/clk/qcom/gdsc.c | 20 +++++++++++++++++++- drivers/clk/qcom/gdsc.h | 5 +++++ 2 files changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c index c7f109b..b802ecf 100644 --- a/drivers/clk/qcom/gdsc.c +++ b/drivers/clk/qcom/gdsc.c @@ -89,6 +89,9 @@ static int gdsc_enable(struct generic_pm_domain *domain) struct gdsc *sc = domain_to_gdsc(domain); int ret; + if (sc->root_clk) + clk_prepare_enable(sc->root_clk); + ret = gdsc_toggle_logic(sc, true); if (ret) return ret; @@ -106,9 +109,15 @@ static int gdsc_enable(struct generic_pm_domain *domain) static int gdsc_disable(struct generic_pm_domain *domain) { + int ret; struct gdsc *sc = domain_to_gdsc(domain); - return gdsc_toggle_logic(sc, false); + ret = gdsc_toggle_logic(sc, false); + + if (sc->root_clk) + clk_disable_unprepare(sc->root_clk); + + return ret; } static int gdsc_attach(struct generic_pm_domain *domain, struct device *dev) @@ -133,6 +142,15 @@ static int gdsc_attach(struct generic_pm_domain *domain, struct device *dev) goto fail; } } + + if (sc->root_con_id) { + sc->root_clk = clk_get(dev, sc->root_con_id); + if (IS_ERR(sc->root_clk)) { + dev_err(dev, "failed to get root clock\n"); + return PTR_ERR(sc->root_clk); + } + } + return 0; fail: pm_clk_destroy(dev); diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h index 68bcda3..cbd95e4 100644 --- a/drivers/clk/qcom/gdsc.h +++ b/drivers/clk/qcom/gdsc.h @@ -17,6 +17,7 @@ #include #include +struct clk; struct regmap; /** @@ -24,12 +25,16 @@ struct regmap; * @pd: generic power domain * @regmap: regmap for MMIO accesses * @gdscr: gsdc control register + * @root_con_id: root clock to be enabled + * @root_clk: clk handle for the root clk * @con_ids: List of clocks to be controlled for the gdsc */ struct gdsc { struct generic_pm_domain pd; struct regmap *regmap; unsigned int gdscr; + char *root_con_id; + struct clk *root_clk; const char *con_ids[]; };