From patchwork Fri Nov 20 08:35:09 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Gross X-Patchwork-Id: 7665761 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: X-Original-To: patchwork-linux-arm-msm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 95E3DBF90C for ; Fri, 20 Nov 2015 08:36:36 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0241E203F7 for ; Fri, 20 Nov 2015 08:36:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2800620437 for ; Fri, 20 Nov 2015 08:36:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1162268AbbKTIfs (ORCPT ); Fri, 20 Nov 2015 03:35:48 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:39979 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1162258AbbKTIfl (ORCPT ); Fri, 20 Nov 2015 03:35:41 -0500 Received: from smtp.codeaurora.org (localhost [127.0.0.1]) by smtp.codeaurora.org (Postfix) with ESMTP id 610BD1401B0; Fri, 20 Nov 2015 08:35:40 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 486) id 5174C1401B5; Fri, 20 Nov 2015 08:35:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from localhost (rrcs-67-52-129-61.west.biz.rr.com [67.52.129.61]) (using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) (Authenticated sender: agross@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id CE21A1401B0; Fri, 20 Nov 2015 08:35:39 +0000 (UTC) From: Andy Gross To: linux-arm-msm@vger.kernel.org Cc: Felipe Balbi , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-usb@vger.kernel.org, Greg KH , devicetree@vger.kernel.org, Kishon Vijay Abraham I , Andy Gross Subject: [PATCH 4/4] Documentation: usb: dwc3: qcom: Add TCSR mux usage Date: Fri, 20 Nov 2015 02:35:09 -0600 Message-Id: <1448008509-8913-5-git-send-email-agross@codeaurora.org> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1448008509-8913-1-git-send-email-agross@codeaurora.org> References: <1448008509-8913-1-git-send-email-agross@codeaurora.org> X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds documentation for the optional syscon-tcsr property in the Qualcomm DWC3 node. The syscon-tcsr specifies the register and bit used to configure the TCSR USB phy mux register. Signed-off-by: Andy Gross Acked-by: Rob Herring --- Documentation/devicetree/bindings/usb/qcom,dwc3.txt | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.txt b/Documentation/devicetree/bindings/usb/qcom,dwc3.txt index ca164e7..dfa222d 100644 --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.txt +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.txt @@ -8,6 +8,10 @@ Required properties: "core" Master/Core clock, have to be >= 125 MHz for SS operation and >= 60MHz for HS operation +Optional properties: +- syscon-tcsr Specifies TCSR handle, register offset, and bit position for + configuring the phy mux setting. + Optional clocks: "iface" System bus AXI clock. Not present on all platforms "sleep" Sleep clock, used when USB3 core goes into low @@ -22,6 +26,11 @@ Documentation/devicetree/bindings/phy/qcom,dwc3-usb-phy.txt Example device nodes: + tcsr: syscon@1a400000 { + compatible = "qcom,tcsr-ipq8064", "syscon"; + reg = <0x1a400000 0x100>; + }; + hs_phy: phy@100f8800 { compatible = "qcom,dwc3-hs-usb-phy"; reg = <0x100f8800 0x30>; @@ -51,6 +60,8 @@ Example device nodes: ranges; + syscon-tcsr = <&tcsr 0xb0 0x1>; + status = "ok"; dwc3@10000000 {