From patchwork Wed May 11 14:15:53 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Gross X-Patchwork-Id: 9071091 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: X-Original-To: patchwork-linux-arm-msm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id A9473BF29F for ; Wed, 11 May 2016 14:19:26 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B47C820154 for ; Wed, 11 May 2016 14:19:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1F0BF200F2 for ; Wed, 11 May 2016 14:19:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932200AbcEKOR7 (ORCPT ); Wed, 11 May 2016 10:17:59 -0400 Received: from mail-oi0-f46.google.com ([209.85.218.46]:35232 "EHLO mail-oi0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932139AbcEKOR5 (ORCPT ); Wed, 11 May 2016 10:17:57 -0400 Received: by mail-oi0-f46.google.com with SMTP id x19so69571444oix.2 for ; Wed, 11 May 2016 07:17:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=MWB0nAU7NbK6a9pA8TB2OdiSTuTH67+CYqZESuZIM48=; b=IusITjJKiAv29NpprYQMVrnlV7WN07QmxhEpuxTxNGw1X1YhdhpSQgsMV9NAGXS4mc n5ACkhUDROCkYhqj17fSTSv5cJyaAyKWQI4/nHv1t1wtYGvsJReQlasZp+c4fvzb+O/p mEoC29Nq1vMvYqM39Is/A/vbe0c3FSzNS91nk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=MWB0nAU7NbK6a9pA8TB2OdiSTuTH67+CYqZESuZIM48=; b=MmtglxWloyFcVen0NRLeSlXWgpZUT0mAx9HbnoLEL1l2497HrIdH+RRnclPngHvcl2 oQs3FoYl17W4PXve/htRP6imIYRGgRbyNuLNwJv07HmrxRxF183gK4CJ8qAuTgNCmdrJ FDQusdD2LRPvwi7usJgs/0jH4zULwF+XVA0phZMNt0hWZZLE/s3nz6kPJUWwi3dETQIS q6oqY6SMZIkQgDvJtHL51Avq7w5XYW1RBhT1V8c8GvCk5sMgP/7EDCVgOkAAVDbb39tR QjVTp2fwhX6+JtmQvZvLJJFpV8N7xRgkQeHBeD04qZrMvYQ+ULNBRCFQeatTgPUVmvyX PoyQ== X-Gm-Message-State: AOPr4FXyRxjEC36BfuL5oprERIi1UhnfjqauUU283deVEfViPGZ6cRwlKzCrNLwPP6YljHtr X-Received: by 10.157.38.200 with SMTP id i8mr1959240otd.150.1462976276652; Wed, 11 May 2016 07:17:56 -0700 (PDT) Received: from localhost ([2602:306:c558:19b0:68a6:b401:fd49:9ae6]) by smtp.gmail.com with ESMTPSA id c2sm2232106obl.18.2016.05.11.07.17.56 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Wed, 11 May 2016 07:17:56 -0700 (PDT) From: Andy Gross To: linux-arm-msm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Bjorn Andersson , Stephen Boyd , jilai wang , Andy Gross Subject: [Patch v4 3/8] firmware: qcom: scm: Use atomic SCM for cold boot Date: Wed, 11 May 2016 09:15:53 -0500 Message-Id: <1462976158-26016-4-git-send-email-andy.gross@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1462976158-26016-1-git-send-email-andy.gross@linaro.org> References: <1462976158-26016-1-git-send-email-andy.gross@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Spam-Status: No, score=-8.2 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch changes the cold_set_boot_addr function to use atomic SCM calls. cold_set_boot_addr required adding qcom_scm_call_atomic2 to support the two arguments going to the smc call. Using atomic removes the need for memory allocation and instead places all arguments in registers. Signed-off-by: Andy Gross Acked-by: Bjorn Andersson --- drivers/firmware/qcom_scm-32.c | 63 ++++++++++++++++++++++++++++++------------ 1 file changed, 45 insertions(+), 18 deletions(-) diff --git a/drivers/firmware/qcom_scm-32.c b/drivers/firmware/qcom_scm-32.c index 0883292..5be6a12 100644 --- a/drivers/firmware/qcom_scm-32.c +++ b/drivers/firmware/qcom_scm-32.c @@ -342,6 +342,41 @@ static s32 qcom_scm_call_atomic1(u32 svc, u32 cmd, u32 arg1) return r0; } +/** + * qcom_scm_call_atomic2() - Send an atomic SCM command with two arguments + * @svc_id: service identifier + * @cmd_id: command identifier + * @arg1: first argument + * @arg2: second argument + * + * This shall only be used with commands that are guaranteed to be + * uninterruptable, atomic and SMP safe. + */ +static s32 qcom_scm_call_atomic2(u32 svc, u32 cmd, u32 arg1, u32 arg2) +{ + int context_id; + + register u32 r0 asm("r0") = SCM_ATOMIC(svc, cmd, 2); + register u32 r1 asm("r1") = (u32)&context_id; + register u32 r2 asm("r2") = arg1; + register u32 r3 asm("r3") = arg2; + + asm volatile( + __asmeq("%0", "r0") + __asmeq("%1", "r0") + __asmeq("%2", "r1") + __asmeq("%3", "r2") + __asmeq("%4", "r3") +#ifdef REQUIRES_SEC + ".arch_extension sec\n" +#endif + "smc #0 @ switch to secure world\n" + : "=r" (r0) + : "r" (r0), "r" (r1), "r" (r2), "r" (r3) + ); + return r0; +} + u32 qcom_scm_get_version(void) { int context_id; @@ -378,22 +413,6 @@ u32 qcom_scm_get_version(void) } EXPORT_SYMBOL(qcom_scm_get_version); -/* - * Set the cold/warm boot address for one of the CPU cores. - */ -static int qcom_scm_set_boot_addr(u32 addr, int flags) -{ - struct { - __le32 flags; - __le32 addr; - } cmd; - - cmd.addr = cpu_to_le32(addr); - cmd.flags = cpu_to_le32(flags); - return qcom_scm_call(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_ADDR, - &cmd, sizeof(cmd), NULL, 0); -} - /** * qcom_scm_set_cold_boot_addr() - Set the cold boot address for cpus * @entry: Entry point function for the cpus @@ -423,7 +442,8 @@ int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus) set_cpu_present(cpu, false); } - return qcom_scm_set_boot_addr(virt_to_phys(entry), flags); + return qcom_scm_call_atomic2(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_ADDR, + flags, virt_to_phys(entry)); } /** @@ -439,6 +459,10 @@ int __qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus) int ret; int flags = 0; int cpu; + struct { + __le32 flags; + __le32 addr; + } cmd; /* * Reassign only if we are switching from hotplug entry point @@ -454,7 +478,10 @@ int __qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus) if (!flags) return 0; - ret = qcom_scm_set_boot_addr(virt_to_phys(entry), flags); + cmd.addr = cpu_to_le32(virt_to_phys(entry)); + cmd.flags = cpu_to_le32(flags); + ret = qcom_scm_call(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_ADDR, + &cmd, sizeof(cmd), NULL, 0); if (!ret) { for_each_cpu(cpu, cpus) qcom_scm_wb[cpu].entry = entry;