From patchwork Fri Jun 3 23:25:23 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Gross X-Patchwork-Id: 9154311 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A86DB60751 for ; Fri, 3 Jun 2016 23:28:29 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 99FC928334 for ; Fri, 3 Jun 2016 23:28:29 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8EF1F28345; Fri, 3 Jun 2016 23:28:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3855D28334 for ; Fri, 3 Jun 2016 23:28:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750787AbcFCX14 (ORCPT ); Fri, 3 Jun 2016 19:27:56 -0400 Received: from mail-oi0-f43.google.com ([209.85.218.43]:36474 "EHLO mail-oi0-f43.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750862AbcFCXZs (ORCPT ); Fri, 3 Jun 2016 19:25:48 -0400 Received: by mail-oi0-f43.google.com with SMTP id j1so149676845oih.3 for ; Fri, 03 Jun 2016 16:25:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=GJfJCADfZJe6QfclIwEoYbGejiTf27lGT0YoHDX4wgs=; b=G346xwHz50Hgy2sfb4AyzDxDlBXBy6gHEL6/gP4m9S5AgvRFIqp4+UR9O5YVM/gkz2 PIBDDK9XXXVkI/9a4/nIwlgjGRZShhRWtM/5PDMhALYhgmW8gS2HR4jx0VG/AkBIVdPD b33x0Uy4YvnCfzvarSzfD9AJ0XaWweMcTrTts= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=GJfJCADfZJe6QfclIwEoYbGejiTf27lGT0YoHDX4wgs=; b=EcqNOJcwke35b2k/VrIkWPQBtxRwd8SIR5STIEgG8YtSmkv8+X4MUbXcZ3EIIOaAtp GRyUJ0du8YWvyixN8IGlbZt3wtKHIzk5Y6tF7rQ2tyX4a5aiMuVz9XXRPNvEybsAeAe6 ICAHxh43U6tRf4iS3U9GKgbq/VOWSsSbPjjf2vAoMLmU2A6o4URAkxbqP3uge4gzNL70 KnWmg4EfC/5yLVCNNXbtqiMfnqawDg2sYrIC4WqGDGnfGOnbKtQZ2PoH6U+dgMlDtMpi JWIGYDCmKr4E0jaavFVBBR2kxuFjzrVo+UUqJU+ab6uA9PXMjEugpcd8hmtRyniDymyd ynUw== X-Gm-Message-State: ALyK8tJw3cviMrDLeLlaHXVke2O4HqKnZdeZdKtZJjQBiGmVdJohBvGlSjbJC0FpHXM8T3fH X-Received: by 10.202.192.196 with SMTP id q187mr3461696oif.126.1464996346892; Fri, 03 Jun 2016 16:25:46 -0700 (PDT) Received: from localhost ([2602:306:c558:19b0:a575:d8f4:7700:e330]) by smtp.gmail.com with ESMTPSA id r105sm2527459ota.28.2016.06.03.16.25.46 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Fri, 03 Jun 2016 16:25:46 -0700 (PDT) From: Andy Gross To: linux-arm-msm@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Bjorn Andersson , Stephen Boyd , devicetree@vger.kernel.org, jilai wang , Andy Gross Subject: [Patch v6 03/10] firmware: qcom: scm: Use atomic SCM for cold boot Date: Fri, 3 Jun 2016 18:25:23 -0500 Message-Id: <1464996330-16952-4-git-send-email-andy.gross@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1464996330-16952-1-git-send-email-andy.gross@linaro.org> References: <1464996330-16952-1-git-send-email-andy.gross@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch changes the cold_set_boot_addr function to use atomic SCM calls. cold_set_boot_addr required adding qcom_scm_call_atomic2 to support the two arguments going to the smc call. Using atomic removes the need for memory allocation and instead places all arguments in registers. Signed-off-by: Andy Gross Reviewed-by: Stephen Boyd Acked-by: Bjorn Andersson --- drivers/firmware/qcom_scm-32.c | 63 ++++++++++++++++++++++++++++++------------ 1 file changed, 45 insertions(+), 18 deletions(-) diff --git a/drivers/firmware/qcom_scm-32.c b/drivers/firmware/qcom_scm-32.c index 0883292..5be6a12 100644 --- a/drivers/firmware/qcom_scm-32.c +++ b/drivers/firmware/qcom_scm-32.c @@ -342,6 +342,41 @@ static s32 qcom_scm_call_atomic1(u32 svc, u32 cmd, u32 arg1) return r0; } +/** + * qcom_scm_call_atomic2() - Send an atomic SCM command with two arguments + * @svc_id: service identifier + * @cmd_id: command identifier + * @arg1: first argument + * @arg2: second argument + * + * This shall only be used with commands that are guaranteed to be + * uninterruptable, atomic and SMP safe. + */ +static s32 qcom_scm_call_atomic2(u32 svc, u32 cmd, u32 arg1, u32 arg2) +{ + int context_id; + + register u32 r0 asm("r0") = SCM_ATOMIC(svc, cmd, 2); + register u32 r1 asm("r1") = (u32)&context_id; + register u32 r2 asm("r2") = arg1; + register u32 r3 asm("r3") = arg2; + + asm volatile( + __asmeq("%0", "r0") + __asmeq("%1", "r0") + __asmeq("%2", "r1") + __asmeq("%3", "r2") + __asmeq("%4", "r3") +#ifdef REQUIRES_SEC + ".arch_extension sec\n" +#endif + "smc #0 @ switch to secure world\n" + : "=r" (r0) + : "r" (r0), "r" (r1), "r" (r2), "r" (r3) + ); + return r0; +} + u32 qcom_scm_get_version(void) { int context_id; @@ -378,22 +413,6 @@ u32 qcom_scm_get_version(void) } EXPORT_SYMBOL(qcom_scm_get_version); -/* - * Set the cold/warm boot address for one of the CPU cores. - */ -static int qcom_scm_set_boot_addr(u32 addr, int flags) -{ - struct { - __le32 flags; - __le32 addr; - } cmd; - - cmd.addr = cpu_to_le32(addr); - cmd.flags = cpu_to_le32(flags); - return qcom_scm_call(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_ADDR, - &cmd, sizeof(cmd), NULL, 0); -} - /** * qcom_scm_set_cold_boot_addr() - Set the cold boot address for cpus * @entry: Entry point function for the cpus @@ -423,7 +442,8 @@ int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus) set_cpu_present(cpu, false); } - return qcom_scm_set_boot_addr(virt_to_phys(entry), flags); + return qcom_scm_call_atomic2(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_ADDR, + flags, virt_to_phys(entry)); } /** @@ -439,6 +459,10 @@ int __qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus) int ret; int flags = 0; int cpu; + struct { + __le32 flags; + __le32 addr; + } cmd; /* * Reassign only if we are switching from hotplug entry point @@ -454,7 +478,10 @@ int __qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus) if (!flags) return 0; - ret = qcom_scm_set_boot_addr(virt_to_phys(entry), flags); + cmd.addr = cpu_to_le32(virt_to_phys(entry)); + cmd.flags = cpu_to_le32(flags); + ret = qcom_scm_call(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_ADDR, + &cmd, sizeof(cmd), NULL, 0); if (!ret) { for_each_cpu(cpu, cpus) qcom_scm_wb[cpu].entry = entry;