| Message ID | 1478517877-23733-10-git-send-email-riteshh@codeaurora.org (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Delegated to: | Andy Gross |
| Headers | show |
On 07/11/16 13:24, Ritesh Harjani wrote: > SDHC MSM controller need 2x clock for MCLK at GCC. > Hence make required changes to have 2x clock for > DDR timing modes. > > Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> > --- > drivers/mmc/host/sdhci-msm.c | 17 +++++++++++++++-- > 1 file changed, 15 insertions(+), 2 deletions(-) > > diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c > index ff0915b..220567c 100644 > --- a/drivers/mmc/host/sdhci-msm.c > +++ b/drivers/mmc/host/sdhci-msm.c > @@ -633,6 +633,7 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock) > { > struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); > struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); > + struct mmc_ios curr_ios = host->mmc->ios; > int rc; > > if (!clock) { > @@ -641,11 +642,23 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock) > } > > spin_unlock_irq(&host->lock); > + /* > + * The SDHC requires internal clock frequency to be double the > + * actual clock that will be set for DDR mode. The controller > + * uses the faster clock(100/400MHz) for some of its parts and > + * send the actual required clock (50/200MHz) to the card. > + */ > + if ((curr_ios.timing == MMC_TIMING_UHS_DDR50) || > + (curr_ios.timing == MMC_TIMING_MMC_DDR52) || > + (curr_ios.timing == MMC_TIMING_MMC_HS400)) > + clock *= 2; > + > if (clock != msm_host->clk_rate) { > rc = clk_set_rate(msm_host->clk, clock); > if (rc) { > - pr_err("%s: Failed to set clock at rate %u\n", > - mmc_hostname(host->mmc), clock); > + pr_err("%s: Failed to set clock at rate %u at timing %d\n", > + mmc_hostname(host->mmc), clock, > + curr_ios.timing); > spin_lock_irq(&host->lock); > goto out; > } > -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index ff0915b..220567c 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -633,6 +633,7 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock) { struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); + struct mmc_ios curr_ios = host->mmc->ios; int rc; if (!clock) { @@ -641,11 +642,23 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock) } spin_unlock_irq(&host->lock); + /* + * The SDHC requires internal clock frequency to be double the + * actual clock that will be set for DDR mode. The controller + * uses the faster clock(100/400MHz) for some of its parts and + * send the actual required clock (50/200MHz) to the card. + */ + if ((curr_ios.timing == MMC_TIMING_UHS_DDR50) || + (curr_ios.timing == MMC_TIMING_MMC_DDR52) || + (curr_ios.timing == MMC_TIMING_MMC_HS400)) + clock *= 2; + if (clock != msm_host->clk_rate) { rc = clk_set_rate(msm_host->clk, clock); if (rc) { - pr_err("%s: Failed to set clock at rate %u\n", - mmc_hostname(host->mmc), clock); + pr_err("%s: Failed to set clock at rate %u at timing %d\n", + mmc_hostname(host->mmc), clock, + curr_ios.timing); spin_lock_irq(&host->lock); goto out; }
SDHC MSM controller need 2x clock for MCLK at GCC. Hence make required changes to have 2x clock for DDR timing modes. Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org> --- drivers/mmc/host/sdhci-msm.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-)