From patchwork Mon Nov 7 11:24:32 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ritesh Harjani X-Patchwork-Id: 9414845 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9237360512 for ; Mon, 7 Nov 2016 11:34:42 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8322728CCF for ; Mon, 7 Nov 2016 11:34:42 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 77C5528CD1; Mon, 7 Nov 2016 11:34:42 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 22E3D28CCF for ; Mon, 7 Nov 2016 11:34:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750912AbcKGLek (ORCPT ); Mon, 7 Nov 2016 06:34:40 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:38988 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751296AbcKGLeh (ORCPT ); Mon, 7 Nov 2016 06:34:37 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 7A9DE61269; Mon, 7 Nov 2016 11:26:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1478517988; bh=XYXB5XnGr3HPPRgEDOyM6QFZ7A+ugA+UNye6DR3fK1Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=E8gyst5GlGi2EF/6fokT1rAYp5tktSrWUxP5WEUTqGnKpDF01dEtBUfY1OJftcTIO gDpkfXLJV0GZ5WWNxawpAvXFpAel8Q9CNrDsiNc1S4WySXg+gALY26R8VaXSM2cRhx N2FL8u3N5CzZXCd6FSN09+FSJFtOeRidnEjIcHY0= Received: from rharjani-linux.qualcomm.com (unknown [202.46.23.54]) (using TLSv1.1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: riteshh@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 3DA55611C3; Mon, 7 Nov 2016 11:26:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1478517987; bh=XYXB5XnGr3HPPRgEDOyM6QFZ7A+ugA+UNye6DR3fK1Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NufQ0xO6XuuSJ8HD4LDR4EiFkCevIserCv6nFi4sQ2BCIH1409esK7tynLhRZcdZj vTnV0kL1LmsWvJB2JBTPKQwnRCMHxNfEKfYgGDu07RR1+JbAihhq3aG1OE+XDbVQfY ceLshE0rCgREx4TS/10nNy7P0aVd3kuMtmNIBPn4= DMARC-Filter: OpenDMARC Filter v1.3.1 smtp.codeaurora.org 3DA55611C3 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=pass smtp.mailfrom=riteshh@codeaurora.org From: Ritesh Harjani To: ulf.hansson@linaro.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, shawn.lin@rock-chips.com, sboyd@codeaurora.org Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, david.brown@linaro.org, andy.gross@linaro.org, linux-arm-msm@vger.kernel.org, georgi.djakov@linaro.org, alex.lemberg@sandisk.com, mateusz.nowak@intel.com, Yuliy.Izrailov@sandisk.com, asutoshd@codeaurora.org, kdorfman@codeaurora.org, david.griego@linaro.org, stummala@codeaurora.org, venkatg@codeaurora.org, rnayak@codeaurora.org, pramod.gurav@linaro.org, Ritesh Harjani Subject: [PATCH v6 09/14] mmc: sdhci-msm: Add clock changes for DDR mode. Date: Mon, 7 Nov 2016 16:54:32 +0530 Message-Id: <1478517877-23733-10-git-send-email-riteshh@codeaurora.org> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1478517877-23733-1-git-send-email-riteshh@codeaurora.org> References: <1478517877-23733-1-git-send-email-riteshh@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP SDHC MSM controller need 2x clock for MCLK at GCC. Hence make required changes to have 2x clock for DDR timing modes. Signed-off-by: Ritesh Harjani Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci-msm.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index ff0915b..220567c 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -633,6 +633,7 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock) { struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); + struct mmc_ios curr_ios = host->mmc->ios; int rc; if (!clock) { @@ -641,11 +642,23 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock) } spin_unlock_irq(&host->lock); + /* + * The SDHC requires internal clock frequency to be double the + * actual clock that will be set for DDR mode. The controller + * uses the faster clock(100/400MHz) for some of its parts and + * send the actual required clock (50/200MHz) to the card. + */ + if ((curr_ios.timing == MMC_TIMING_UHS_DDR50) || + (curr_ios.timing == MMC_TIMING_MMC_DDR52) || + (curr_ios.timing == MMC_TIMING_MMC_HS400)) + clock *= 2; + if (clock != msm_host->clk_rate) { rc = clk_set_rate(msm_host->clk, clock); if (rc) { - pr_err("%s: Failed to set clock at rate %u\n", - mmc_hostname(host->mmc), clock); + pr_err("%s: Failed to set clock at rate %u at timing %d\n", + mmc_hostname(host->mmc), clock, + curr_ios.timing); spin_lock_irq(&host->lock); goto out; }