From patchwork Mon Nov 21 06:37:21 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ritesh Harjani X-Patchwork-Id: 9438925 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 8296D60235 for ; Mon, 21 Nov 2016 06:39:19 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 743572842E for ; Mon, 21 Nov 2016 06:39:19 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 684F42844E; Mon, 21 Nov 2016 06:39:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1D8412842E for ; Mon, 21 Nov 2016 06:39:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753494AbcKUGjR (ORCPT ); Mon, 21 Nov 2016 01:39:17 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:46694 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752149AbcKUGjP (ORCPT ); Mon, 21 Nov 2016 01:39:15 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id CE1D6614EC; Mon, 21 Nov 2016 06:39:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1479710355; bh=4HJRMGOcskboVsiHTsxGWi7uI4evopl4ZtHK7XRSKHA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AXd0j9TOIeN5QmuCDfwwhFmMO971XkCjRAkcbv9abaluB/0bZj06F49D82QrCJGMe HEeRYXP7BAarqhe5H4HhnxLRdBmw3peLbih+rYB5JJP2iKB3T4H5C1NSS5LZeqHqd/ 1nLkWOZWJIjnGs6pjNs7cJG6obl1UOEGSt62e2VA= Received: from rharjani-linux.qualcomm.com (unknown [202.46.23.54]) (using TLSv1.1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: riteshh@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 6A01E614E0; Mon, 21 Nov 2016 06:39:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1479710352; bh=4HJRMGOcskboVsiHTsxGWi7uI4evopl4ZtHK7XRSKHA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bgpAV+WGj/hGPJGLEqXIMz2VLzVpl7JXGoZqjo6h99ZdDsVwo5GN4fIwnD3lZLEbO WIwp3X+GL60MXU1SIgM5x/WWbfekJdxZWOSf1YZxECgB5L8btSVTopD8tj7A5f8IuU 1BFmwK4XGmrINghGH6ZFBad84wiMRVsjqceY9o74= DMARC-Filter: OpenDMARC Filter v1.3.1 smtp.codeaurora.org 6A01E614E0 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=pass smtp.mailfrom=riteshh@codeaurora.org From: Ritesh Harjani To: ulf.hansson@linaro.org, linux-mmc@vger.kernel.org, adrian.hunter@intel.com, sboyd@codeaurora.org, andy.gross@linaro.org Cc: shawn.lin@rock-chips.com, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, david.brown@linaro.org, linux-arm-msm@vger.kernel.org, georgi.djakov@linaro.org, alex.lemberg@sandisk.com, mateusz.nowak@intel.com, Yuliy.Izrailov@sandisk.com, asutoshd@codeaurora.org, david.griego@linaro.org, stummala@codeaurora.org, venkatg@codeaurora.org, rnayak@codeaurora.org, pramod.gurav@linaro.org, jeremymc@redhat.com, Ritesh Harjani Subject: [PATCH v9 11/16] mmc: sdhci-msm: Add clock changes for DDR mode. Date: Mon, 21 Nov 2016 12:07:21 +0530 Message-Id: <1479710246-26676-12-git-send-email-riteshh@codeaurora.org> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1479710246-26676-1-git-send-email-riteshh@codeaurora.org> References: <1479710246-26676-1-git-send-email-riteshh@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP SDHC MSM controller need 2x clock for MCLK at GCC. Hence make required changes to have 2x clock for DDR timing modes. Signed-off-by: Ritesh Harjani Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci-msm.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 00759ef..c50cee8 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -610,6 +610,7 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock) { struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); + struct mmc_ios curr_ios = host->mmc->ios; int rc; if (!clock) { @@ -618,16 +619,28 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock) } spin_unlock_irq(&host->lock); + /* + * The SDHC requires internal clock frequency to be double the + * actual clock that will be set for DDR mode. The controller + * uses the faster clock(100/400MHz) for some of its parts and + * send the actual required clock (50/200MHz) to the card. + */ + if (curr_ios.timing == MMC_TIMING_UHS_DDR50 || + curr_ios.timing == MMC_TIMING_MMC_DDR52 || + curr_ios.timing == MMC_TIMING_MMC_HS400) + clock *= 2; rc = clk_set_rate(msm_host->clk, clock); if (rc) { - pr_err("%s: Failed to set clock at rate %u\n", - mmc_hostname(host->mmc), clock); + pr_err("%s: Failed to set clock at rate %u at timing %d\n", + mmc_hostname(host->mmc), clock, + curr_ios.timing); goto out_lock; } msm_host->clk_rate = clock; - pr_debug("%s: Setting clock at rate %lu\n", - mmc_hostname(host->mmc), clk_get_rate(msm_host->clk)); + pr_debug("%s: Setting clock at rate %lu at timing %d\n", + mmc_hostname(host->mmc), clk_get_rate(msm_host->clk), + curr_ios.timing); out_lock: spin_lock_irq(&host->lock);