From patchwork Tue Dec 20 05:53:19 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ritesh Harjani X-Patchwork-Id: 9481161 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id DD779601C0 for ; Tue, 20 Dec 2016 05:54:22 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CF54D27D4D for ; Tue, 20 Dec 2016 05:54:22 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C2EC52849D; Tue, 20 Dec 2016 05:54:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2FBDF27D4D for ; Tue, 20 Dec 2016 05:54:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933678AbcLTFyU (ORCPT ); Tue, 20 Dec 2016 00:54:20 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:42510 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933630AbcLTFx5 (ORCPT ); Tue, 20 Dec 2016 00:53:57 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 0823D6159A; Tue, 20 Dec 2016 05:53:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1482213236; bh=vlOC7G75gtRqjtLFCDWPJwKxzFrqIVE81WIT06LilP8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GhkJT4kgXFezx5dMr+p8NROwt/2XRUVL28UwnzbAt9kXDOcDMPtlOnW8ZiM4+ttxR lXpSc/UTJoDnPGS7Z5O4BcTAhkASa4dg+32+8ipvGwyzPJm62rAVUaap202k9NaoEf 4gTTLebIPFVLfr+UPmlnz24YhKSNmL6sHEbcsBgQ= Received: from rharjani-linux.qualcomm.com (unknown [202.46.23.54]) (using TLSv1.1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: riteshh@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id BB74D61389; Tue, 20 Dec 2016 05:53:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1482213233; bh=vlOC7G75gtRqjtLFCDWPJwKxzFrqIVE81WIT06LilP8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JLh/1IFkJATJWt+xhIRM5zsgKZyLAauBejkOh0UbeaZ9D81ofVaX6RDTuQ+dpNvSP a9BPczU5AXWe035qYmFbGgbSzjHEJRru3G2P+qVkkR+7upOMEXegY0z1J07I1xua/V KPVTkY7vrQABbGh49wxzLS+axROsdDAXfrkjHD68= DMARC-Filter: OpenDMARC Filter v1.3.1 smtp.codeaurora.org BB74D61389 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=pass smtp.mailfrom=riteshh@codeaurora.org From: Ritesh Harjani To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, shawn.lin@rock-chips.com, linux-kernel@vger.kernel.org, stummala@codeaurora.org, georgi.djakov@linaro.org, linux-arm-msm@vger.kernel.org, pramod.gurav@linaro.org, jeremymc@redhat.com, venkatg@codeaurora.org, asutoshd@codeaurora.org, Ritesh Harjani Subject: [PATCH 4/4] mmc: sdhci-msm: provide enhanced_strobe mode feature support Date: Tue, 20 Dec 2016 11:23:19 +0530 Message-Id: <1482213199-29152-5-git-send-email-riteshh@codeaurora.org> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1482213199-29152-1-git-send-email-riteshh@codeaurora.org> References: <1482213199-29152-1-git-send-email-riteshh@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This provide support for enhanced_strobe feature to sdhci-msm. Signed-off-by: Ritesh Harjani --- drivers/mmc/host/sdhci-msm.c | 32 +++++++++++++++++++++++--------- 1 file changed, 23 insertions(+), 9 deletions(-) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 32879b8..d092a16 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -102,6 +102,7 @@ #define CORE_DDR_200_CFG 0x184 #define CORE_CDC_T4_DLY_SEL BIT(0) +#define CORE_CMDIN_RCLK_EN BIT(1) #define CORE_START_CDC_TRAFFIC BIT(6) #define CORE_VENDOR_SPEC3 0x1b0 #define CORE_PWRSAVE_DLL BIT(3) @@ -579,6 +580,7 @@ static int sdhci_msm_cdclp533_calibration(struct sdhci_host *host) static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host) { + struct mmc_host *mmc = host->mmc; u32 dll_status, config; int ret; @@ -593,6 +595,12 @@ static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host) */ writel_relaxed(DDR_CONFIG_POR_VAL, host->ioaddr + CORE_DDR_CONFIG); + if (mmc->ios.enhanced_strobe) { + config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG); + config |= CORE_CMDIN_RCLK_EN; + writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG); + } + config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2); config |= CORE_DDR_CAL_EN; writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2); @@ -627,6 +635,7 @@ static int sdhci_msm_hs400_dll_calibration(struct sdhci_host *host) { struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); + struct mmc_host *mmc = host->mmc; int ret; u32 config; @@ -640,14 +649,17 @@ static int sdhci_msm_hs400_dll_calibration(struct sdhci_host *host) if (ret) goto out; - /* Set the selected phase in delay line hw block */ - ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase); - if (ret) - goto out; + if (!mmc->ios.enhanced_strobe) { + /* Set the selected phase in delay line hw block */ + ret = msm_config_cm_dll_phase(host, + msm_host->saved_tuning_phase); + if (ret) + goto out; + config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); + config |= CORE_CMD_DAT_TRACK_SEL; + writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); + } - config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); - config |= CORE_CMD_DAT_TRACK_SEL; - writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); if (msm_host->use_cdclp533) ret = sdhci_msm_cdclp533_calibration(host); else @@ -802,7 +814,8 @@ static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host, spin_unlock_irq(&host->lock); /* CDCLP533 HW calibration is only required for HS400 mode*/ if (host->clock > CORE_FREQ_100MHZ && - msm_host->tuning_done && !msm_host->calibration_done && + (msm_host->tuning_done || mmc->ios.enhanced_strobe) && + !msm_host->calibration_done && mmc->ios.timing == MMC_TIMING_MMC_HS400) if (!sdhci_msm_hs400_dll_calibration(host)) msm_host->calibration_done = true; @@ -941,7 +954,8 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock) * Select HS400 mode using the HC_SELECT_IN from VENDOR SPEC * register */ - if (msm_host->tuning_done && !msm_host->calibration_done) { + if ((msm_host->tuning_done || curr_ios.enhanced_strobe) && + !msm_host->calibration_done) { /* * Write 0x6 to HC_SELECT_IN and 1 to HC_SELECT_IN_EN * field in VENDOR_SPEC_FUNC