diff mbox

[V4,1/6] clk: qcom: SDHCI enablement on Nexus 5X / 6P

Message ID 1485508205-1904-2-git-send-email-jeremymc@redhat.com (mailing list archive)
State Not Applicable, archived
Delegated to: Andy Gross
Headers show

Commit Message

Jeremy McNicoll Jan. 27, 2017, 9:10 a.m. UTC
Add missing clock branch to enable onboard storage
for msm899(2/4).

Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com>
---
 drivers/clk/qcom/gcc-msm8994.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

Comments

kernel test robot Jan. 27, 2017, 5 p.m. UTC | #1
Hi Jeremy,

[auto build test ERROR on robh/for-next]
[also build test ERROR on v4.10-rc5 next-20170125]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Jeremy-McNicoll/Enable-onboard-SDHCI-for-Nexus-5X-msm8992/20170127-171555
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: arm-allyesconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
        wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        make.cross ARCH=arm 

Note: the linux-review/Jeremy-McNicoll/Enable-onboard-SDHCI-for-Nexus-5X-msm8992/20170127-171555 HEAD 2d5a2b64c15910ea3011d16aac5fe40f7edae2fd builds fine.
      It only hurts bisectibility.

All errors (new ones prefixed by >>):

>> drivers/clk/qcom/gcc-msm8994.c:2251:3: error: 'GCC_SDCC1_AHB_CLK' undeclared here (not in a function)
     [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
      ^~~~~~~~~~~~~~~~~
>> drivers/clk/qcom/gcc-msm8994.c:2251:3: error: array index in initializer not of integer type
   drivers/clk/qcom/gcc-msm8994.c:2251:3: note: (near initialization for 'gcc_msm8994_clocks')

vim +/GCC_SDCC1_AHB_CLK +2251 drivers/clk/qcom/gcc-msm8994.c

  2245		[GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
  2246		[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
  2247		[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
  2248		[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
  2249		[GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
  2250		[GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
> 2251		[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
  2252		[GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr,
  2253		[GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
  2254		[GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation
Stephen Boyd Jan. 27, 2017, 9:33 p.m. UTC | #2
On 01/27, Jeremy McNicoll wrote:
> Add missing clock branch to enable onboard storage
> for msm899(2/4).
> 
> Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com>
> ---

Applied to clk-next
diff mbox

Patch

diff --git a/drivers/clk/qcom/gcc-msm8994.c b/drivers/clk/qcom/gcc-msm8994.c
index 8afd830..7983288 100644
--- a/drivers/clk/qcom/gcc-msm8994.c
+++ b/drivers/clk/qcom/gcc-msm8994.c
@@ -1888,6 +1888,23 @@  static struct clk_branch gcc_sdcc1_apps_clk = {
 	},
 };
 
+static struct clk_branch gcc_sdcc1_ahb_clk = {
+	.halt_reg = 0x04c8,
+	.clkr = {
+		.enable_reg = 0x04c8,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data)
+		{
+			.name = "gcc_sdcc1_ahb_clk",
+			.parent_names = (const char *[]){
+				"periph_noc_clk_src",
+			},
+			.num_parents = 1,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
 static struct clk_branch gcc_sdcc2_apps_clk = {
 	.halt_reg = 0x0504,
 	.clkr = {
@@ -2231,6 +2248,7 @@  static struct clk_regmap *gcc_msm8994_clocks[] = {
 	[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
 	[GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
 	[GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
+	[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
 	[GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr,
 	[GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
 	[GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,