From patchwork Tue Jun 27 09:45:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 9811209 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 57F6460351 for ; Tue, 27 Jun 2017 09:49:01 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C188425404 for ; Tue, 27 Jun 2017 09:48:53 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B623928613; Tue, 27 Jun 2017 09:48:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B192B25404 for ; Tue, 27 Jun 2017 09:48:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752606AbdF0Jsv (ORCPT ); Tue, 27 Jun 2017 05:48:51 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:51888 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752766AbdF0Jq0 (ORCPT ); Tue, 27 Jun 2017 05:46:26 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id D8A46609FD; Tue, 27 Jun 2017 09:46:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1498556785; bh=szZDYpUIc0JluHkr9NHW1M1FqH5XThIeauLCi/y9jrs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MY4bBRr+lhi7wC1579N7UXVem7g19OJFltO8b1uEcpOTMUqwUtkTpIiZG2mvtxaLy Rg1l1jgQbAMIDKGb1Jt54q78LGAr4GYB2LRSP1V0BGUIzmtXJI8yyJMyyCHga7V/0m enti/MeBk+f0x8PwcOm8KThJZZW3hbWWfbBHI9Jg= Received: from varda-linux.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: varada@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 9141D6090C; Tue, 27 Jun 2017 09:46:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1498556784; bh=szZDYpUIc0JluHkr9NHW1M1FqH5XThIeauLCi/y9jrs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SZ+1J2N7/z6uOE86dylgmabitdd6DB/y6wzmHkpt1pKOJSvy8Uc+4OwsvUrSnbQ0O FDCoWGfvQePqduEJlGnm5xxGTgHRsdT+PQ006YyyxyF4F0COL9Tjgl/hxyr8H0M8iq jN+VmHL6rsGtibfZlyyiWqTJxr1aHm8PKb4pjGpk= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 9141D6090C Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=varada@codeaurora.org From: Varadarajan Narayanan To: broonie@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, andy.gross@linaro.org, david.brown@linaro.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org Cc: Varadarajan Narayanan , Matthew McClintock Subject: [PATCH v4 11/14] spi: qup: allow block mode to generate multiple transactions Date: Tue, 27 Jun 2017 15:15:28 +0530 Message-Id: <1498556731-13087-12-git-send-email-varada@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1498556731-13087-1-git-send-email-varada@codeaurora.org> References: <1498556731-13087-1-git-send-email-varada@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This let's you write more to the SPI bus than 64K-1 which is important if the block size of a SPI device is >= 64K or some other device wants to do something larger. This has the benefit of completely removing spi_message from the spi-qup transactions Signed-off-by: Matthew McClintock Signed-off-by: Varadarajan Narayanan --- drivers/spi/spi-qup.c | 128 +++++++++++++++++++++++++++++++------------------- 1 file changed, 80 insertions(+), 48 deletions(-) diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c index 37b51e3..026f25e 100644 --- a/drivers/spi/spi-qup.c +++ b/drivers/spi/spi-qup.c @@ -120,7 +120,7 @@ #define SPI_NUM_CHIPSELECTS 4 -#define SPI_MAX_DMA_XFER (SZ_64K - 64) +#define SPI_MAX_XFER (SZ_64K - 64) /* high speed mode is when bus rate is greater then 26MHz */ #define SPI_HS_MIN_RATE 26000000 @@ -151,6 +151,8 @@ struct spi_qup { int n_words; int tx_bytes; int rx_bytes; + const u8 *tx_buf; + u8 *rx_buf; int qup_v1; int mode; @@ -175,6 +177,12 @@ static inline bool spi_qup_is_dma_xfer(int mode) return false; } +/* get's the transaction size length */ +static inline unsigned int spi_qup_len(struct spi_qup *controller) +{ + return controller->n_words * controller->w_size; +} + static inline bool spi_qup_is_valid_state(struct spi_qup *controller) { u32 opstate = readl_relaxed(controller->base + QUP_STATE); @@ -227,10 +235,9 @@ static int spi_qup_set_state(struct spi_qup *controller, u32 state) return 0; } -static void spi_qup_read_from_fifo(struct spi_qup *controller, - struct spi_transfer *xfer, u32 num_words) +static void spi_qup_read_from_fifo(struct spi_qup *controller, u32 num_words) { - u8 *rx_buf = xfer->rx_buf; + u8 *rx_buf = controller->rx_buf; int i, shift, num_bytes; u32 word; @@ -238,8 +245,9 @@ static void spi_qup_read_from_fifo(struct spi_qup *controller, word = readl_relaxed(controller->base + QUP_INPUT_FIFO); - num_bytes = min_t(int, xfer->len - controller->rx_bytes, - controller->w_size); + num_bytes = min_t(int, spi_qup_len(controller) - + controller->rx_bytes, + controller->w_size); if (!rx_buf) { controller->rx_bytes += num_bytes; @@ -260,13 +268,12 @@ static void spi_qup_read_from_fifo(struct spi_qup *controller, } } -static void spi_qup_read(struct spi_qup *controller, - struct spi_transfer *xfer) +static void spi_qup_read(struct spi_qup *controller) { u32 remainder, words_per_block, num_words; bool is_block_mode = controller->mode == QUP_IO_M_MODE_BLOCK; - remainder = DIV_ROUND_UP(xfer->len - controller->rx_bytes, + remainder = DIV_ROUND_UP(spi_qup_len(controller) - controller->rx_bytes, controller->w_size); words_per_block = controller->in_blk_sz >> 2; @@ -287,7 +294,7 @@ static void spi_qup_read(struct spi_qup *controller, } /* read up to the maximum transfer size available */ - spi_qup_read_from_fifo(controller, xfer, num_words); + spi_qup_read_from_fifo(controller, num_words); remainder -= num_words; @@ -309,18 +316,18 @@ static void spi_qup_read(struct spi_qup *controller, } -static void spi_qup_write_to_fifo(struct spi_qup *controller, - struct spi_transfer *xfer, u32 num_words) +static void spi_qup_write_to_fifo(struct spi_qup *controller, u32 num_words) { - const u8 *tx_buf = xfer->tx_buf; + const u8 *tx_buf = controller->tx_buf; int i, num_bytes; u32 word, data; for (; num_words; num_words--) { word = 0; - num_bytes = min_t(int, xfer->len - controller->tx_bytes, - controller->w_size); + num_bytes = min_t(int, spi_qup_len(controller) - + controller->tx_bytes, + controller->w_size); if (tx_buf) for (i = 0; i < num_bytes; i++) { data = tx_buf[controller->tx_bytes + i]; @@ -338,13 +345,12 @@ static void spi_qup_dma_done(void *data) complete(data); } -static void spi_qup_write(struct spi_qup *controller, - struct spi_transfer *xfer) +static void spi_qup_write(struct spi_qup *controller) { bool is_block_mode = controller->mode == QUP_IO_M_MODE_BLOCK; u32 remainder, words_per_block, num_words; - remainder = DIV_ROUND_UP(xfer->len - controller->tx_bytes, + remainder = DIV_ROUND_UP(spi_qup_len(controller) - controller->tx_bytes, controller->w_size); words_per_block = controller->out_blk_sz >> 2; @@ -364,7 +370,7 @@ static void spi_qup_write(struct spi_qup *controller, num_words = 1; } - spi_qup_write_to_fifo(controller, xfer, num_words); + spi_qup_write_to_fifo(controller, num_words); remainder -= num_words; @@ -469,36 +475,62 @@ static int spi_qup_do_pio(struct spi_device *spi, struct spi_transfer *xfer, { struct spi_master *master = spi->master; struct spi_qup *qup = spi_master_get_devdata(master); - int ret; + int ret, n_words, iterations, offset = 0; - ret = spi_qup_io_config(spi, xfer); - if (ret) - return ret; + n_words = qup->n_words; + iterations = n_words / SPI_MAX_XFER; /* round down */ + qup->rx_buf = xfer->rx_buf; + qup->tx_buf = xfer->tx_buf; - ret = spi_qup_set_state(qup, QUP_STATE_RUN); - if (ret) { - dev_warn(qup->dev, "cannot set RUN state\n"); - return ret; - } + do { + if (iterations) + qup->n_words = SPI_MAX_XFER; + else + qup->n_words = n_words % SPI_MAX_XFER; - ret = spi_qup_set_state(qup, QUP_STATE_PAUSE); - if (ret) { - dev_warn(qup->dev, "cannot set PAUSE state\n"); - return ret; - } + if (qup->tx_buf && offset) + qup->tx_buf = xfer->tx_buf + offset * SPI_MAX_XFER; - if (qup->mode == QUP_IO_M_MODE_FIFO) - spi_qup_write(qup, xfer); + if (qup->rx_buf && offset) + qup->rx_buf = xfer->rx_buf + offset * SPI_MAX_XFER; - ret = spi_qup_set_state(qup, QUP_STATE_RUN); - if (ret) { - dev_warn(qup->dev, "%s(%d): cannot set RUN state\n", - __func__, __LINE__); - return ret; - } + /* + * if the transaction is small enough, we need + * to fallback to FIFO mode + */ + if (qup->n_words <= (qup->in_fifo_sz / sizeof(u32))) + qup->mode = QUP_IO_M_MODE_FIFO; - if (!wait_for_completion_timeout(&qup->done, timeout)) - return -ETIMEDOUT; + ret = spi_qup_io_config(spi, xfer); + if (ret) + return ret; + + ret = spi_qup_set_state(qup, QUP_STATE_RUN); + if (ret) { + dev_warn(qup->dev, "cannot set RUN state\n"); + return ret; + } + + ret = spi_qup_set_state(qup, QUP_STATE_PAUSE); + if (ret) { + dev_warn(qup->dev, "cannot set PAUSE state\n"); + return ret; + } + + if (qup->mode == QUP_IO_M_MODE_FIFO) + spi_qup_write(qup); + + ret = spi_qup_set_state(qup, QUP_STATE_RUN); + if (ret) { + dev_warn(qup->dev, "cannot set RUN state\n"); + return ret; + } + + if (!wait_for_completion_timeout(&qup->done, timeout)) + return -ETIMEDOUT; + + offset++; + } while (iterations--); return 0; } @@ -506,7 +538,6 @@ static int spi_qup_do_pio(struct spi_device *spi, struct spi_transfer *xfer, static irqreturn_t spi_qup_qup_irq(int irq, void *dev_id) { struct spi_qup *controller = dev_id; - struct spi_transfer *xfer = controller->xfer; u32 opflags, qup_err, spi_err; int error = 0; @@ -543,10 +574,10 @@ static irqreturn_t spi_qup_qup_irq(int irq, void *dev_id) writel_relaxed(opflags, controller->base + QUP_OPERATIONAL); } else { if (opflags & QUP_OP_IN_SERVICE_FLAG) - spi_qup_read(controller, xfer); + spi_qup_read(controller); if (opflags & QUP_OP_OUT_SERVICE_FLAG) - spi_qup_write(controller, xfer); + spi_qup_write(controller); } if ((opflags & QUP_OP_MAX_INPUT_DONE_FLAG) || error) @@ -756,7 +787,8 @@ static int spi_qup_transfer_one(struct spi_master *master, return ret; timeout = DIV_ROUND_UP(xfer->speed_hz, MSEC_PER_SEC); - timeout = DIV_ROUND_UP(xfer->len * 8, timeout); + timeout = DIV_ROUND_UP(min_t(unsigned long, SPI_MAX_XFER, + xfer->len) * 8, timeout); timeout = 100 * msecs_to_jiffies(timeout); if (spi_qup_is_dma_xfer(controller->mode)) @@ -961,7 +993,7 @@ static int spi_qup_probe(struct platform_device *pdev) master->dev.of_node = pdev->dev.of_node; master->auto_runtime_pm = true; master->dma_alignment = dma_get_cache_alignment(); - master->max_dma_len = SPI_MAX_DMA_XFER; + master->max_dma_len = SPI_MAX_XFER; platform_set_drvdata(pdev, master);