From patchwork Tue Jun 27 09:45:30 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 9811191 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id E001460351 for ; Tue, 27 Jun 2017 09:47:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2F0DA28503 for ; Tue, 27 Jun 2017 09:47:48 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2358128613; Tue, 27 Jun 2017 09:47:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id ADA9828503 for ; Tue, 27 Jun 2017 09:47:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752484AbdF0Jrq (ORCPT ); Tue, 27 Jun 2017 05:47:46 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:52548 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752797AbdF0Jqf (ORCPT ); Tue, 27 Jun 2017 05:46:35 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 9D76E60D92; Tue, 27 Jun 2017 09:46:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1498556794; bh=RoQ8Y6ENlAXM7/xRvO1iD8JJE7McmxLPHEpnGlVdGUo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=S7IV/cGRN3A5S5aHQhE/tM3LmN7J1JtpyyM9TMPfkb1tgqFu84oKds2ItfxhwNMDG mBK5WUjKMsUIZ4EwwwIehIMRarHSOcdQJg4Ru3fgMkTzdPQBeGqwIw3q+6Giah8080 FiRziXDXxe3fVuMK6I5ZZmO5Sebz7ochoN/hajoU= Received: from varda-linux.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: varada@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 6A70A607CE; Tue, 27 Jun 2017 09:46:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1498556792; bh=RoQ8Y6ENlAXM7/xRvO1iD8JJE7McmxLPHEpnGlVdGUo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=l/kzGNcTtw5UoGVLU/6jAq+LjWO7iDtTUwRgmRn8jaCYdP60zhIR0W6QeeoKTKpey ube//2ij/+vODY6YsW0V3KLXAgizTAQAcy5UY8rvAQKT55KoSGLgR1hmQLI5Iltaoy NXIypo/o/1OXis/P8sFOYs1gLwZgir/lT2mCUZj4= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 6A70A607CE Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=varada@codeaurora.org From: Varadarajan Narayanan To: broonie@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, andy.gross@linaro.org, david.brown@linaro.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org Cc: Varadarajan Narayanan , Matthew McClintock Subject: [PATCH v4 13/14] spi: qup: allow multiple DMA transactions per spi xfer Date: Tue, 27 Jun 2017 15:15:30 +0530 Message-Id: <1498556731-13087-14-git-send-email-varada@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1498556731-13087-1-git-send-email-varada@codeaurora.org> References: <1498556731-13087-1-git-send-email-varada@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Much like the block mode changes, we are breaking up DMA transactions into 64K chunks so we can reset the QUP engine. Signed-off-by: Matthew McClintock Signed-off-by: Varadarajan Narayanan --- drivers/spi/spi-qup.c | 104 ++++++++++++++++++++++++++++++++++++-------------- 1 file changed, 76 insertions(+), 28 deletions(-) diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c index 2423ee5..a39a0d2 100644 --- a/drivers/spi/spi-qup.c +++ b/drivers/spi/spi-qup.c @@ -417,50 +417,98 @@ static void spi_qup_dma_terminate(struct spi_master *master, dmaengine_terminate_all(master->dma_rx); } +static u32 spi_qup_sgl_get_nents_len(struct scatterlist *sgl, u32 max, + u32 *nents) +{ + struct scatterlist *sg; + u32 total = 0; + + *nents = 0; + + for (sg = sgl; sg; sg = sg_next(sg)) { + unsigned int len = sg_dma_len(sg); + + /* check for overflow as well as limit */ + if (((total + len) < total) || ((total + len) > max)) + break; + + total += len; + (*nents)++; + } + + return total; +} + static int spi_qup_do_dma(struct spi_device *spi, struct spi_transfer *xfer, unsigned long timeout) { struct spi_master *master = spi->master; struct spi_qup *qup = spi_master_get_devdata(master); + struct scatterlist *tx_sgl, *rx_sgl; int ret; - ret = spi_qup_io_config(spi, xfer); - if (ret) - return ret; + rx_sgl = xfer->rx_sg.sgl; + tx_sgl = xfer->tx_sg.sgl; - /* before issuing the descriptors, set the QUP to run */ - ret = spi_qup_set_state(qup, QUP_STATE_RUN); - if (ret) { - dev_warn(qup->dev, "%s(%d): cannot set RUN state\n", - __func__, __LINE__); - return ret; - } + do { + u32 rx_nents, tx_nents; + + if (rx_sgl) + qup->n_words = spi_qup_sgl_get_nents_len(rx_sgl, + SPI_MAX_XFER, &rx_nents) / qup->w_size; + if (tx_sgl) + qup->n_words = spi_qup_sgl_get_nents_len(tx_sgl, + SPI_MAX_XFER, &tx_nents) / qup->w_size; + if (!qup->n_words) + return -EIO; - if (xfer->rx_buf) { - ret = spi_qup_prep_sg(master, xfer->rx_sg.sgl, - xfer->rx_sg.nents, DMA_DEV_TO_MEM, - spi_qup_dma_done, &qup->rxc); + ret = spi_qup_io_config(spi, xfer); if (ret) return ret; - dma_async_issue_pending(master->dma_rx); - } - - if (xfer->tx_buf) { - ret = spi_qup_prep_sg(master, xfer->tx_sg.sgl, - xfer->tx_sg.nents, DMA_MEM_TO_DEV, - spi_qup_dma_done, &qup->txc); - if (ret) + /* before issuing the descriptors, set the QUP to run */ + ret = spi_qup_set_state(qup, QUP_STATE_RUN); + if (ret) { + dev_warn(qup->dev, "cannot set RUN state\n"); return ret; + } + if (rx_sgl) { + ret = spi_qup_prep_sg(master, rx_sgl, rx_nents, + DMA_DEV_TO_MEM, + spi_qup_dma_done, &qup->rxc); + if (ret) + return ret; + dma_async_issue_pending(master->dma_rx); + } - dma_async_issue_pending(master->dma_tx); - } + if (tx_sgl) { + ret = spi_qup_prep_sg(master, tx_sgl, tx_nents, + DMA_MEM_TO_DEV, + spi_qup_dma_done, &qup->txc); + if (ret) + return ret; + + dma_async_issue_pending(master->dma_tx); + } + + if (rx_sgl && + !wait_for_completion_timeout(&qup->rxc, timeout)) { + pr_emerg(" rx timed out\n"); + return -ETIMEDOUT; + } + + if (tx_sgl && + !wait_for_completion_timeout(&qup->txc, timeout)) { + pr_emerg(" tx timed out\n"); + return -ETIMEDOUT; + } - if (xfer->rx_buf && !wait_for_completion_timeout(&qup->rxc, timeout)) - return -ETIMEDOUT; + for (; rx_sgl && rx_nents--; rx_sgl = sg_next(rx_sgl)) + ; + for (; tx_sgl && tx_nents--; tx_sgl = sg_next(tx_sgl)) + ; - if (xfer->tx_buf && !wait_for_completion_timeout(&qup->txc, timeout)) - return -ETIMEDOUT; + } while (rx_sgl || tx_sgl); return 0; }