From patchwork Mon Jul 17 12:04:02 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 9844761 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9E8FA60386 for ; Mon, 17 Jul 2017 12:05:26 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 90E6126E97 for ; Mon, 17 Jul 2017 12:05:26 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 859522823D; Mon, 17 Jul 2017 12:05:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1EBF526E97 for ; Mon, 17 Jul 2017 12:05:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751489AbdGQMFT (ORCPT ); Mon, 17 Jul 2017 08:05:19 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:48996 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751280AbdGQMFP (ORCPT ); Mon, 17 Jul 2017 08:05:15 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 1351A6143D; Mon, 17 Jul 2017 12:05:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1500293114; bh=5FchY5YlooVJA2yEHIif6LsBDLBBixedZeNodeJqShQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Mdf0mW77SCqTyaVDkv8mLYnqzj9bZ6YMg9FRH2XeGR/FJYlM+xlkUUCPp1JkZpUDR yGO3L61JLpifkhKOqXCbksbrzxJkoSGCi52VZiGaruK7dBoF49dehvUAjDw7xTz5y5 Z2xgaPdcE7jTbF4kSDa1ozDjXPqt1dn2PwhRJ8hE= Received: from varda-linux.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: varada@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id E6BEC61422; Mon, 17 Jul 2017 12:05:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1500293112; bh=5FchY5YlooVJA2yEHIif6LsBDLBBixedZeNodeJqShQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Cfy2eqKwfOXs5lzoaxBkM6f05yqXZmstKuO/LnqaFWhDt9KmvhS8TI+nOaWzT4GH8 soCT88lEV5Ete2RPm9Tpwa2aEZwDEHe7K7RwZt0Of0RHWB2y8O0q7Bk1iCQQfcZnH3 L/pWs3vTxiM1fN7CAgNHu/DQ8IwlWPgL0HsQeNjo= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org E6BEC61422 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=varada@codeaurora.org From: Varadarajan Narayanan To: bhelgaas@google.com, robh+dt@kernel.org, mark.rutland@arm.com, svarbanov@mm-sol.com, kishon@ti.com, sboyd@codeaurora.org, vivek.gautam@codeaurora.org, fengguang.wu@intel.com, weiyongjun1@huawei.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: Varadarajan Narayanan Subject: [PATCH 6/7] dt-bindings: pci: qcom: Add support for IPQ8074 Date: Mon, 17 Jul 2017 17:34:02 +0530 Message-Id: <1500293043-1887-7-git-send-email-varada@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1500293043-1887-1-git-send-email-varada@codeaurora.org> References: <1500293043-1887-1-git-send-email-varada@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add support for the IPQ8074 PCIe controller. IPQ8074 supports Gen 1/2, one lane, two PCIe root complex with support for MSI and legacy interrupts, and it conforms to PCI Express Base 2.1 specification. Signed-off-by: Varadarajan Narayanan --- .../devicetree/bindings/pci/qcom,pcie.txt | 67 ++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index 9d418b7..643bcc2 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -9,6 +9,7 @@ - "qcom,pcie-apq8084" for apq8084 - "qcom,pcie-msm8996" for msm8996 or apq8096 - "qcom,pcie-ipq4019" for ipq4019 + - "qcom,pcie-ipq8074" for ipq8074 - reg: Usage: required @@ -261,3 +262,69 @@ pinctrl-0 = <&pcie0_pins_default>; pinctrl-names = "default"; }; + +* Example for ipq8074 + pcie0: pci@20000000 { + compatible = "qcom,pcie-ipq8074"; + reg = <0x20000000 0xf1d + 0x20000F20 0xa8 + 0x80000 0x2000 + 0x20100000 0x1000>; + reg-names = "dbi", "elbi", "parf", "config"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + + phys = <&pciephy_0>; + phy-names = "pciephy"; + + ranges = <0x81000000 0 0x20200000 0x20200000 + 0 0x00100000 /* downstream I/O */ + 0x82000000 0 0x20300000 0x20300000 + 0 0x00d00000>; /* non-prefetchable memory */ + + interrupts = <0 52 0>; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 75 + IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 78 + IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 79 + IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 83 + IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, + <&gcc GCC_PCIE0_AXI_M_CLK>, + <&gcc GCC_PCIE0_AXI_S_CLK>, + <&gcc GCC_PCIE0_AHB_CLK>, + <&gcc GCC_PCIE0_AUX_CLK>; + clock-names = "sys_noc", + "axi_m", + "axi_s", + "ahb", + "aux"; + + resets = <&gcc GCC_PCIE0_PIPE_ARES>, + <&gcc GCC_PCIE0_SLEEP_ARES>, + <&gcc GCC_PCIE0_CORE_STICKY_ARES>, + <&gcc GCC_PCIE0_AXI_MASTER_ARES>, + <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, + <&gcc GCC_PCIE0_AHB_ARES>, + <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>; + reset-names = "pipe", + "sleep", + "sticky", + "axi_m", + "axi_s", + "ahb", + "axi_m_sticky"; + + perst-gpio = <&tlmm 58 1>; + status = "disabled"; + };