From patchwork Tue Jan 16 10:57:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manu Gautam X-Patchwork-Id: 10166505 X-Patchwork-Delegate: agross@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 5997A600CA for ; Tue, 16 Jan 2018 11:01:38 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 53D4A284C8 for ; Tue, 16 Jan 2018 11:01:38 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4DED0284AA; Tue, 16 Jan 2018 11:01:38 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 41C6F28619 for ; Tue, 16 Jan 2018 11:01:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751449AbeAPK6c (ORCPT ); Tue, 16 Jan 2018 05:58:32 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:47988 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751871AbeAPK63 (ORCPT ); Tue, 16 Jan 2018 05:58:29 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 48F436095F; Tue, 16 Jan 2018 10:58:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1516100309; bh=nSxeFMk51GeUAkcvChDa8912fjrbGJYYiecvJtvgQTM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CEdziRMl3m02JQrWVg5th6+7iKqEQf61oZMmngxLQNv0jUdD9qT7YZeSq0uyqtmAh LdGZmzVn0K/I2LamoR2N8dtwvQNgpyfYTjbojuyYOstlo5qaPq5lNjLdCEgNFqmrL3 E81oay5YU0mYwK6Y97QGo8MSX0z5NVZnYJCkL2tE= Received: from mgautam-linux.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: mgautam@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id F1CC460585; Tue, 16 Jan 2018 10:58:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1516100308; bh=nSxeFMk51GeUAkcvChDa8912fjrbGJYYiecvJtvgQTM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YNxi4/bC9KSVLklaDYYGmgH0BwT09JSeP+PI9hffww18bWNs8+etMV9rGeBdJpMQo M+pPaykKSWxW2bS3z5eRUwE3UG6D/IzPnqWi3CKfpeefZXYvklKannfArPRxsn+Z0f jPFXXD8m6sGBLMF42DPo4zpkHevzJbaVd8fg+yjQ= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org F1CC460585 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=mgautam@codeaurora.org From: Manu Gautam To: Kishon Vijay Abraham I Cc: linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, Manu Gautam , Vivek Gautam , Stephen Boyd , Yoshihiro Shimoda , linux-kernel@vger.kernel.org (open list:GENERIC PHY FRAMEWORK) Subject: [PATCH v5 09/17] phy: qcom-qusb2: Add support for QUSB2 V2 version Date: Tue, 16 Jan 2018 16:27:04 +0530 Message-Id: <1516100232-18623-10-git-send-email-mgautam@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1516100232-18623-1-git-send-email-mgautam@codeaurora.org> References: <1516100232-18623-1-git-send-email-mgautam@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Use register layout to add additional registers present on QUSB2 PHY V2 version for PHY initialization. Other than new registers on V2, following two register's offset and bit definitions are different: POWERDOWN control and PLL_STATUS. Signed-off-by: Manu Gautam Reviewed-by: Vivek Gautam --- drivers/phy/qualcomm/phy-qcom-qusb2.c | 64 +++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c index b65635f..9b0d1ff 100644 --- a/drivers/phy/qualcomm/phy-qcom-qusb2.c +++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c @@ -40,15 +40,34 @@ /* QUSB2PHY_PLL_STATUS register bits */ #define PLL_LOCKED BIT(5) +/* QUSB2PHY_PLL_COMMON_STATUS_ONE register bits */ +#define CORE_READY_STATUS BIT(0) + /* QUSB2PHY_PORT_POWERDOWN register bits */ #define CLAMP_N_EN BIT(5) #define FREEZIO_N BIT(1) #define POWER_DOWN BIT(0) +/* QUSB2PHY_PWR_CTRL1 register bits */ +#define PWR_CTRL1_VREF_SUPPLY_TRIM BIT(5) +#define PWR_CTRL1_CLAMP_N_EN BIT(1) + #define QUSB2PHY_REFCLK_ENABLE BIT(0) #define PHY_CLK_SCHEME_SEL BIT(0) +#define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO 0x04 +#define QUSB2PHY_PLL_CLOCK_INVERTERS 0x18c +#define QUSB2PHY_PLL_CMODE 0x2c +#define QUSB2PHY_PLL_LOCK_DELAY 0x184 +#define QUSB2PHY_PLL_DIGITAL_TIMERS_TWO 0xb4 +#define QUSB2PHY_PLL_BIAS_CONTROL_1 0x194 +#define QUSB2PHY_PLL_BIAS_CONTROL_2 0x198 +#define QUSB2PHY_PWR_CTRL2 0x214 +#define QUSB2PHY_IMP_CTRL1 0x220 +#define QUSB2PHY_IMP_CTRL2 0x224 +#define QUSB2PHY_CHG_CTRL2 0x23c + struct qusb2_phy_init_tbl { unsigned int offset; unsigned int val; @@ -113,6 +132,38 @@ enum qusb2phy_reg_layout { QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00), }; +static const unsigned int qusb2_v2_regs_layout[] = { + [QUSB2PHY_PLL_STATUS] = 0x1a0, + [QUSB2PHY_PORT_TUNE1] = 0x240, + [QUSB2PHY_PORT_TUNE2] = 0x244, + [QUSB2PHY_PORT_TUNE3] = 0x248, + [QUSB2PHY_PORT_TUNE4] = 0x24c, + [QUSB2PHY_PORT_TUNE5] = 0x250, + [QUSB2PHY_PORT_TEST2] = 0x258, + [QUSB2PHY_PORT_POWERDOWN] = 0x210, +}; + +static const struct qusb2_phy_init_tbl qusb2_v2_init_tbl[] = { + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_ANALOG_CONTROLS_TWO, 0x03), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CLOCK_INVERTERS, 0x7c), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CMODE, 0x80), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_LOCK_DELAY, 0x0a), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_DIGITAL_TIMERS_TWO, 0x19), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_BIAS_CONTROL_1, 0x40), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_BIAS_CONTROL_2, 0x20), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PWR_CTRL2, 0x21), + QUSB2_PHY_INIT_CFG(QUSB2PHY_IMP_CTRL1, 0x0), + QUSB2_PHY_INIT_CFG(QUSB2PHY_IMP_CTRL2, 0x58), + + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0x30), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x29), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0xca), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0x04), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE5, 0x03), + + QUSB2_PHY_INIT_CFG(QUSB2PHY_CHG_CTRL2, 0x0), +}; + struct qusb2_phy_cfg { const struct qusb2_phy_init_tbl *tbl; /* number of entries in the table */ @@ -142,6 +193,16 @@ struct qusb2_phy_cfg { .mask_core_ready = PLL_LOCKED, }; +static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = { + .tbl = qusb2_v2_init_tbl, + .tbl_num = ARRAY_SIZE(qusb2_v2_init_tbl), + .regs = qusb2_v2_regs_layout, + + .disable_ctrl = (PWR_CTRL1_VREF_SUPPLY_TRIM | PWR_CTRL1_CLAMP_N_EN | + POWER_DOWN), + .mask_core_ready = CORE_READY_STATUS, +}; + static const char * const qusb2_phy_vreg_names[] = { "vdda-pll", "vdda-phy-dpdm", }; @@ -429,6 +490,9 @@ static int qusb2_phy_exit(struct phy *phy) { .compatible = "qcom,msm8996-qusb2-phy", .data = &msm8996_phy_cfg, + }, { + .compatible = "qcom,qusb2-v2-phy", + .data = &qusb2_v2_phy_cfg, }, { }, };