From patchwork Fri Mar 23 06:11:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manu Gautam X-Patchwork-Id: 10302755 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A372460385 for ; Fri, 23 Mar 2018 06:12:41 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 89B7728B60 for ; Fri, 23 Mar 2018 06:12:41 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7DCE228B62; Fri, 23 Mar 2018 06:12:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2D41A28B63 for ; Fri, 23 Mar 2018 06:12:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751897AbeCWGM3 (ORCPT ); Fri, 23 Mar 2018 02:12:29 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:42332 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751409AbeCWGMZ (ORCPT ); Fri, 23 Mar 2018 02:12:25 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id DA76A607EB; Fri, 23 Mar 2018 06:12:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521785544; bh=HVAVApqd5KPyAHGKq39WGnNyysuuyikhAnOo4Mt0Abc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kcKPMLzjuPRwAAFFcZaseO5lqYFGVj5t8xyp1MxIlVu3n9SwxJx5NmE3ouwSsT9xr n/ohjdTEfgw/fxJK4qPeRqcGFb3pDk7FWKP7PodOD/KRaWgVNCb4i7YqI40trYm5lF wpIiOb7WovEnmTAYaAwvHcd7zpo/qgZgW2ZmTN1I= Received: from mgautam-linux.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: mgautam@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id CCF036055D; Fri, 23 Mar 2018 06:12:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521785544; bh=HVAVApqd5KPyAHGKq39WGnNyysuuyikhAnOo4Mt0Abc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kcKPMLzjuPRwAAFFcZaseO5lqYFGVj5t8xyp1MxIlVu3n9SwxJx5NmE3ouwSsT9xr n/ohjdTEfgw/fxJK4qPeRqcGFb3pDk7FWKP7PodOD/KRaWgVNCb4i7YqI40trYm5lF wpIiOb7WovEnmTAYaAwvHcd7zpo/qgZgW2ZmTN1I= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org CCF036055D Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=mgautam@codeaurora.org From: Manu Gautam To: Kishon Vijay Abraham I Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Rob Herring , linux-arm-msm@vger.kernel.org, Manu Gautam , Vivek Gautam , Stephen Boyd , Krzysztof Kozlowski Subject: [PATCH v3 6/6] phy: qcom-qusb2: Add QUSB2 PHYs support for sdm845 Date: Fri, 23 Mar 2018 11:41:27 +0530 Message-Id: <1521785487-29866-7-git-send-email-mgautam@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1521785487-29866-1-git-send-email-mgautam@codeaurora.org> References: <1521785487-29866-1-git-send-email-mgautam@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP There are two QUSB2 PHYs present on sdm845. Update PHY registers programming for both the PHYs related to electrical parameters to improve eye diagram. Signed-off-by: Manu Gautam Reviewed-by: Evan Green --- drivers/phy/qualcomm/phy-qcom-qusb2.c | 39 +++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c index 40fdef8..020cbb2 100644 --- a/drivers/phy/qualcomm/phy-qcom-qusb2.c +++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c @@ -174,6 +174,27 @@ enum qusb2phy_reg_layout { QUSB2_PHY_INIT_CFG(QUSB2PHY_CHG_CTRL2, 0x0), }; +static const struct qusb2_phy_init_tbl sdm845_init_tbl_1[] = { + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_ANALOG_CONTROLS_TWO, 0x03), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CLOCK_INVERTERS, 0x7c), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CMODE, 0x80), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_LOCK_DELAY, 0x0a), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_DIGITAL_TIMERS_TWO, 0x19), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_BIAS_CONTROL_1, 0x40), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_BIAS_CONTROL_2, 0x20), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PWR_CTRL2, 0x21), + QUSB2_PHY_INIT_CFG(QUSB2PHY_IMP_CTRL1, 0x8), + QUSB2_PHY_INIT_CFG(QUSB2PHY_IMP_CTRL2, 0x58), + + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0x45), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x29), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0xca), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0x04), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE5, 0x03), + + QUSB2_PHY_INIT_CFG(QUSB2PHY_CHG_CTRL2, 0x0), +}; + struct qusb2_phy_cfg { const struct qusb2_phy_init_tbl *tbl; /* number of entries in the table */ @@ -220,6 +241,18 @@ struct qusb2_phy_cfg { .autoresume_en = BIT(0), }; +static const struct qusb2_phy_cfg sdm845_phy_cfg_1 = { + .tbl = sdm845_init_tbl_1, + .tbl_num = ARRAY_SIZE(sdm845_init_tbl_1), + .regs = qusb2_v2_regs_layout, + + .disable_ctrl = (PWR_CTRL1_VREF_SUPPLY_TRIM | PWR_CTRL1_CLAMP_N_EN | + POWER_DOWN), + .mask_core_ready = CORE_READY_STATUS, + .has_pll_override = true, + .autoresume_en = BIT(0), +}; + static const char * const qusb2_phy_vreg_names[] = { "vdda-pll", "vdda-phy-dpdm", }; @@ -649,6 +682,12 @@ static int qusb2_phy_exit(struct phy *phy) }, { .compatible = "qcom,qusb2-v2-phy", .data = &qusb2_v2_phy_cfg, + }, { + .compatible = "qcom,sdm845-qusb2-phy-1", + .data = &sdm845_phy_cfg_1, + }, { + .compatible = "qcom,sdm845-qusb2-phy-2", + .data = &qusb2_v2_phy_cfg, }, { }, };