From patchwork Thu Mar 29 11:04:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manu Gautam X-Patchwork-Id: 10314941 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id AEAB16037E for ; Thu, 29 Mar 2018 11:07:43 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A7B132A2FA for ; Thu, 29 Mar 2018 11:07:43 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A61392A30A; Thu, 29 Mar 2018 11:07:43 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 18CC32A2FA for ; Thu, 29 Mar 2018 11:07:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752427AbeC2LGA (ORCPT ); Thu, 29 Mar 2018 07:06:00 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:43226 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752365AbeC2LF5 (ORCPT ); Thu, 29 Mar 2018 07:05:57 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 4989C60F5C; Thu, 29 Mar 2018 11:05:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1522321556; bh=0WMp6EOSuq9dnbs3lD72e8h5U7IkKETevqTAS89LUv0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eG8hH8f87cB3uOG9AWQVrPxWtKJoUXwxEf//dnGavsKHxG35iLWkrMAwVCMSIJKoB H9TcGwBEbo2TGjPFHIqRcEO+ZobWrTyuLBPypuD7zXCq5YaSoRaTxAO8IkseGLrPUK bpnQkHc1asWFdsRVgw1fExNCDvD7V8NftsK6PT0I= Received: from mgautam-linux.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: mgautam@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id E67E860F71; Thu, 29 Mar 2018 11:05:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1522321554; bh=0WMp6EOSuq9dnbs3lD72e8h5U7IkKETevqTAS89LUv0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=gU/d1cFfZrUS+e0sWD1j8vRvLP395jnPESgGMaCRxkbruHJLHD2aotfLk+vq99wWR zOiBtE9S5gr6lPrZ45yWOQ56jybDMNWBcgfSWiFqZDNo3k96gEbS4tTtA7h+ekBDH+ irCsJA+V4YOoB/ZR4zPtpdsHIS+Q3fglKTQ6WBkI= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org E67E860F71 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=mgautam@codeaurora.org From: Manu Gautam To: Kishon Vijay Abraham I , robh@kernel.org, sboyd@codeaurora.org Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, vivek.gautam@codeaurora.org, evgreen@chromium.org, dianders@chromium.org, linux-arm-msm@vger.kernel.org, Manu Gautam , Andy Gross , David Brown , Michael Turquette , Stephen Boyd , linux-soc@vger.kernel.org (open list:ARM/QUALCOMM SUPPORT), linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK) Subject: [PATCH v4 1/7] clk: msm8996-gcc: change halt check for USB/PCIE pipe_clk Date: Thu, 29 Mar 2018 16:34:20 +0530 Message-Id: <1522321466-21755-2-git-send-email-mgautam@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1522321466-21755-1-git-send-email-mgautam@codeaurora.org> References: <1522321466-21755-1-git-send-email-mgautam@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The USB and PCIE pipe clocks are sourced from external clocks inside the QMP USB/PCIE PHYs. Enabling or disabling of PIPE RCG clocks is dependent on PHY initialization sequence hence update halt_check to BRANCH_HALT_DELAY for these clocks so that clock status bit is not polled when enabling or disabling the clocks. It allows to simplify PHY client driver code which is both user and source of the pipe_clk and avoid error logging related status check on clk_disable/enable. Signed-off-by: Manu Gautam --- drivers/clk/qcom/gcc-msm8996.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c index 5d74512..336d12d 100644 --- a/drivers/clk/qcom/gcc-msm8996.c +++ b/drivers/clk/qcom/gcc-msm8996.c @@ -1418,6 +1418,7 @@ enum { static struct clk_branch gcc_usb3_phy_pipe_clk = { .halt_reg = 0x50004, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x50004, .enable_mask = BIT(0), @@ -2472,6 +2473,7 @@ enum { static struct clk_branch gcc_pcie_0_pipe_clk = { .halt_reg = 0x6b018, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x6b018, .enable_mask = BIT(0), @@ -2547,6 +2549,7 @@ enum { static struct clk_branch gcc_pcie_1_pipe_clk = { .halt_reg = 0x6d018, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x6d018, .enable_mask = BIT(0), @@ -2622,6 +2625,7 @@ enum { static struct clk_branch gcc_pcie_2_pipe_clk = { .halt_reg = 0x6e018, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x6e018, .enable_mask = BIT(0),